projectapheleia / avlLinks
Apheleia Verification Library. A Python based HDL verification library sitting on top of cocotb
☆42Updated 2 weeks ago
Alternatives and similar repositories for avl
Users that are interested in avl are comparing it to the libraries listed below
Sorting:
- RTLMeter benchmark suite☆28Updated 2 weeks ago
- SpiceBind – spice inside HDL simulator☆56Updated 6 months ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆42Updated last year
- An automatic clock gating utility☆51Updated 8 months ago
- SystemVerilog Linter based on pyslang☆31Updated 7 months ago
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- CMake based hardware build system☆35Updated 2 weeks ago
- A command-line tool for displaying vcd waveforms.☆65Updated last year
- ☆33Updated 11 months ago
- Determines the modules declared and instantiated in a SystemVerilog file☆49Updated last year
- Rust Test Bench - write HDL tests in Rust.☆23Updated 3 years ago
- Python library for operations with VCD and other digital wave files☆53Updated last month
- AXI Formal Verification IP☆21Updated 4 years ago
- A SystemVerilog language server based on the Slang library.☆97Updated this week
- design and verification of asynchronous circuits☆42Updated 2 weeks ago
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆26Updated 4 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆21Updated 4 years ago
- Hardware generator debugger☆77Updated last year
- Making cocotb testbenches that bit easier☆36Updated 2 months ago
- ☆38Updated 3 years ago
- Mutation Cover with Yosys (MCY)☆89Updated 3 weeks ago
- A configurable SRAM generator☆56Updated 4 months ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated 10 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆44Updated 2 years ago
- Python interface for cross-calling with HDL☆45Updated last week
- A library and command-line tool for querying a Verilog netlist.☆29Updated 3 years ago
- Prefix tree adder space exploration library☆56Updated last year
- HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-sla…☆25Updated 9 months ago
- VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation deb…☆33Updated last month
- VHDLproc is a VHDL preprocessor☆24Updated 3 years ago