Alternatives and similar repositories for avl

Users that are interested in avl are comparing it to the libraries listed below

• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆43Updated 2 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆51Updated 7 months ago
• themperek / spicebind
  SpiceBind – spice inside HDL simulator
  ☆56Updated 5 months ago
• verilator / rtlmeter
  RTLMeter benchmark suite
  ☆28Updated this week
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 7 months ago
• benbr8 / rstb
  Rust Test Bench - write HDL tests in Rust.
  ☆23Updated 3 years ago
• pulp-platform / svase
  ☆33Updated 11 months ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 10 months ago
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆48Updated last year
• hudson-trading / slang-server
  A SystemVerilog language server based on the Slang library.
  ☆76Updated this week
• Nic30 / pyDigitalWaveTools
  Python library for operations with VCD and other digital wave files
  ☆53Updated last month
• PyFPGA / HDLconv
  HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-sla…
  ☆25Updated 9 months ago
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆36Updated last month
• snishizawa / libretto
  Characterizer
  ☆30Updated 3 weeks ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆43Updated 2 years ago
• broccolimicro / loom
  design and verification of asynchronous circuits
  ☆41Updated 3 weeks ago
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆45Updated this week
• VHDL / Compliance-Tests
  Tests to evaluate the support of VHDL 2008 and VHDL 2019 features
  ☆32Updated 10 months ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• rahulk29 / sram22
  A configurable SRAM generator
  ☆56Updated 3 months ago
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆51Updated last week
• dh73 / A_Formal_Tale_Chapter_I_AMBA
  AXI Formal Verification IP
  ☆21Updated 4 years ago
• wallento / cocotbext-uart
  UART cocotb module
  ☆11Updated 4 years ago
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆65Updated last year
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆76Updated 4 months ago
• antmicro / verilator-uvm-example
  Example of how to use UVM with Verilator
  ☆28Updated last week
• antmicro / sv-bugpoint
  ☆31Updated 3 weeks ago
• tdene / synth_opt_adders
  Prefix tree adder space exploration library
  ☆56Updated last year
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆178Updated this week