Alternatives and similar repositories for uvm-core

Users that are interested in uvm-core are comparing it to the libraries listed below

• accellera / uvm
  ☆56Updated 9 years ago
• raysalemi / Python4RTLVerification
  ☆165Updated 3 years ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆253Updated 7 months ago
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆116Updated last year
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆139Updated last year
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆191Updated 3 years ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆281Updated last week
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆71Updated 4 years ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆126Updated last month
• cluelogic / cluelib
  A generic class library in SystemVerilog
  ☆84Updated 4 years ago
• svunit / svunit
  ☆206Updated 6 months ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆70Updated 4 years ago
• cluelogic / uvm-tutorial-for-candy-lovers
  Source code repo for UVM Tutorial for Candy Lovers
  ☆199Updated 8 years ago
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆201Updated 10 months ago
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆104Updated last year
• chipsalliance / uvm-verilator
  ☆97Updated last year
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆106Updated 4 years ago
• themperek / cocotb-test
  Unit testing for cocotb
  ☆161Updated 3 months ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆94Updated 4 years ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆65Updated last month
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆174Updated last week
• GodelMachine / AHB2
  AMBA AHB 2.0 VIP in SystemVerilog UVM
  ☆154Updated 5 years ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆92Updated last year
• jerralph / riscv-vip
  For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
  ☆63Updated 4 years ago
• gupta409 / Processor-UVM-Verification
  System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
  ☆106Updated 8 months ago
• Practical-UVM-Step-By-Step / Practical-UVM-Step-By-Step
  This is the main repository for all the examples for the book Practical UVM
  ☆202Updated 4 years ago
• amiq-consulting / svaunit
  SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)
  ☆74Updated 4 years ago
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆257Updated last month
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆97Updated 2 months ago
• kumarrishav14 / AXI
  VIP for AXI Protocol
  ☆149Updated 3 years ago