Alternatives and similar repositories for uvm-core

Users that are interested in uvm-core are comparing it to the libraries listed below

• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆252Updated 5 months ago
• raysalemi / Python4RTLVerification
  ☆161Updated 2 years ago
• accellera / uvm
  ☆54Updated 9 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆66Updated 4 years ago
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆113Updated last year
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆102Updated last year
• svunit / svunit
  ☆204Updated 4 months ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆270Updated last year
• hellovimo / uvm_testbench_gen
  Novel GUI Based UVM Testbench Template Builder
  ☆138Updated 4 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-Step-By-Step
  This is the main repository for all the examples for the book Practical UVM
  ☆199Updated 4 years ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆64Updated 4 years ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆138Updated last month
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆136Updated last year
• mayurkubavat / UVM-Examples
  UVM examples and projects
  ☆140Updated 2 weeks ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆89Updated last year
• cluelogic / uvm-tutorial-for-candy-lovers
  Source code repo for UVM Tutorial for Candy Lovers
  ☆192Updated 8 years ago
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆75Updated 3 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆105Updated 3 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆208Updated last year
• cluelogic / cluelib
  A generic class library in SystemVerilog
  ☆84Updated 4 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆92Updated 4 years ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆123Updated last month
• andres-mancera / ethernet_10ge_mac_SV_UVM_tb
  SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
  ☆144Updated 6 years ago
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆202Updated 8 months ago
• GodelMachine / AHB2
  AMBA AHB 2.0 VIP in SystemVerilog UVM
  ☆151Updated 5 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆161Updated 3 weeks ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆214Updated last week
• kumarrishav14 / AXI
  VIP for AXI Protocol
  ☆139Updated 3 years ago
• amiq-consulting / svaunit
  SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)
  ☆74Updated 4 years ago
• naragece / uvm-testbench-tutorial-simple-adder
  A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology
  ☆104Updated 11 years ago