antmicro / topwrapLinks
A Python package for generating HDL wrappers and top modules for HDL sources
☆56Updated this week
Alternatives and similar repositories for topwrap
Users that are interested in topwrap are comparing it to the libraries listed below
Sorting:
- SpiceBind – spice inside HDL simulator☆56Updated 7 months ago
- SystemVerilog Linter based on pyslang☆31Updated 9 months ago
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆80Updated last week
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a log…☆69Updated 4 months ago
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆26Updated 7 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆37Updated 3 years ago
- RISC-V Nox core☆71Updated 6 months ago
- ☆33Updated last year
- Quick'n'dirty FuseSoC+cocotb example☆19Updated last year
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆77Updated 6 months ago
- An open source, parameterized SystemVerilog digital hardware IP library☆33Updated last year
- FPGA250 aboard the eFabless Caravel☆32Updated 5 years ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆65Updated 2 months ago
- ☆58Updated 10 months ago
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 7 months ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- YosysHQ SVA AXI Properties☆43Updated 3 years ago
- submission repository for efabless mpw6 shuttle☆31Updated 2 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆110Updated this week
- Bitstream relocation and manipulation tool.☆51Updated 3 years ago
- Making cocotb testbenches that bit easier☆36Updated 3 months ago
- VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation deb…☆34Updated 3 months ago
- Flip flop setup, hold & metastability explorer tool☆52Updated 3 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆79Updated 3 years ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆42Updated last year
- UART cocotb module☆11Updated 4 years ago
- Open source ISS and logic RISC-V 32 bit project☆60Updated 2 weeks ago
- ☆38Updated 3 years ago
- An open-source HDL register code generator fast enough to run in real time.☆82Updated this week