antmicro / topwrap
A Python package for generating HDL wrappers and top modules for HDL sources
☆32Updated last week
Alternatives and similar repositories for topwrap:
Users that are interested in topwrap are comparing it to the libraries listed below
- SystemVerilog Linter based on pyslang☆30Updated 3 months ago
- ☆31Updated 3 months ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 5 months ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆23Updated 5 months ago
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆17Updated last month
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- ☆33Updated 2 years ago
- RISC-V Nox core☆62Updated last month
- UART models for cocotb☆28Updated 2 years ago
- A compact, configurable RISC-V core☆11Updated last month
- FPGA250 aboard the eFabless Caravel☆29Updated 4 years ago
- cryptography ip-cores in vhdl / verilog☆40Updated 4 years ago
- USB virtual model in C++ for Verilog☆29Updated 6 months ago
- APB UVC ported to Verilator☆11Updated last year
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆10Updated 2 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆26Updated 11 months ago
- VHDLproc is a VHDL preprocessor☆24Updated 2 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- Open source RTL simulation acceleration on commodity hardware☆25Updated 2 years ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆41Updated last year
- ☆27Updated 3 weeks ago
- An automatic clock gating utility☆47Updated 2 weeks ago
- ☆36Updated 2 years ago
- hardware library for hwt (= ipcore repo)☆37Updated 5 months ago
- Open FPGA Modules☆23Updated 6 months ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆54Updated 2 months ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆25Updated 10 months ago
- high level VHDL floating point library for synthesis in fpga☆16Updated 2 months ago