antmicro / topwrap
A Python package for generating HDL wrappers and top modules for HDL sources
☆23Updated last week
Related projects ⓘ
Alternatives and complementary repositories for topwrap
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- Quick'n'dirty FuseSoC+cocotb example☆17Updated 5 months ago
- SystemVerilog Linter based on pyslang☆23Updated 8 months ago
- cryptography ip-cores in vhdl / verilog☆40Updated 3 years ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆47Updated this week
- Making cocotb testbenches that bit easier☆24Updated last week
- Proposed RISC-V Composable Custom Extensions Specification☆67Updated 6 months ago
- Provides automation scripts for building BFMs☆16Updated 3 years ago
- A compact, configurable RISC-V core☆11Updated last week
- Generate address space documentation HTML from compiled SystemRDL input☆47Updated 2 months ago
- ☆36Updated 2 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆30Updated 3 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated 11 months ago
- ☆14Updated this week
- Platform Level Interrupt Controller☆35Updated 6 months ago
- Constrained RAndom Verification Enviroment (CRAVE)☆16Updated last year
- An open-source HDL register code generator fast enough to run in real time.☆37Updated this week
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated last year
- ☆57Updated 3 years ago
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆22Updated this week
- Extended and external tests for Verilator testing☆15Updated last week
- high level VHDL floating point library for synthesis in fpga☆15Updated 4 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆64Updated 2 months ago
- Docker Development Environment for SpinalHDL☆18Updated 3 months ago
- Examples and design pattern for VHDL verification☆15Updated 8 years ago
- ☆20Updated 3 weeks ago
- RISC-V Nox core☆61Updated 3 months ago
- ☆26Updated last year
- ☆29Updated 2 months ago
- ☆33Updated 2 years ago