A Python package for generating HDL wrappers and top modules for HDL sources
☆70Apr 7, 2026Updated this week
Alternatives and similar repositories for topwrap
Users that are interested in topwrap are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Raw image/video data analyzer☆48Jan 29, 2025Updated last year
- ☆35Feb 20, 2026Updated last month
- ☆19Apr 1, 2026Updated last week
- ☆15Oct 2, 2023Updated 2 years ago
- Raptor end-to-end FPGA Compiler and GUI☆96Dec 11, 2024Updated last year
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- ☆19Mar 19, 2026Updated 3 weeks ago
- Library of FPGA architectures☆31Mar 9, 2026Updated last month
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆38May 4, 2024Updated last year
- VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation deb…☆37Nov 6, 2025Updated 5 months ago
- FOMU keystroke injector☆12Aug 7, 2023Updated 2 years ago
- ☆21Apr 2, 2026Updated last week
- ☆38Updated this week
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆27Feb 2, 2026Updated 2 months ago
- Open source Logic Analyzer based on LiteX SoC☆27Apr 12, 2025Updated 11 months ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆32Oct 15, 2024Updated last year
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 4 years ago
- ☆15Mar 9, 2026Updated last month
- KISCV, a KISS principle riscv32i CPU☆28Jan 11, 2025Updated last year
- ☆91Mar 30, 2026Updated last week
- A Python package to use FPGA development tools programmatically.☆146Mar 22, 2025Updated last year
- ☆43Apr 1, 2026Updated last week
- Coverview☆28Jan 29, 2026Updated 2 months ago
- VHDL code generator for AXI4-lite register files☆12May 22, 2024Updated last year
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Hardware Snappy decompressor☆11Sep 11, 2024Updated last year
- A tiny 3-stage RISC-V core written in Chisel.☆16Apr 14, 2023Updated 2 years ago
- Experimental GMSL2 serializer board compatible with Antmicro MIPI CSI video accessories☆20Mar 21, 2025Updated last year
- Universal Memory Interface (UMI)☆157Mar 30, 2026Updated last week
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆30Mar 29, 2013Updated 13 years ago
- Opensource DDR3 Controller☆425Jan 18, 2026Updated 2 months ago
- HTML & Js based VCD viewer☆74Feb 16, 2026Updated last month
- Generate Zynq configurations without using the vendor GUI☆30Jul 5, 2023Updated 2 years ago
- Microarchitectural control flow integrity (𝜇CFI) verification checks whether there exists a control or data flow from instruction's ope…☆16Feb 12, 2026Updated last month
- Wordpress hosting with auto-scaling on Cloudways • AdFully Managed hosting built for WordPress-powered businesses that need reliable, auto-scalable hosting. Cloudways SafeUpdates now available.
- ☆85Mar 26, 2026Updated 2 weeks ago
- RISC-V soft-core PEs for TaPaSCo☆23Jan 30, 2026Updated 2 months ago
- ☆20Mar 10, 2026Updated 3 weeks ago
- Examples and design pattern for VHDL verification☆15Apr 10, 2016Updated 10 years ago
- Framework Open EDA Gui☆73Dec 11, 2024Updated last year
- FPGA for uSDR☆21Mar 27, 2026Updated 2 weeks ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆43Mar 7, 2024Updated 2 years ago