Alternatives and similar repositories for topwrap

Users that are interested in topwrap are comparing it to the libraries listed below

• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated last month
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆18Updated 6 months ago
• TinyTapeout / tinytapeout-ihp-0p1
  Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process
  ☆17Updated 2 months ago
• pulp-platform / svase
  ☆32Updated 5 months ago
• aignacio / mpsoc_example
  ☆59Updated 3 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆29Updated 2 years ago
• craigjb / fuse-zynq
  Generate Zynq configurations without using the vendor GUI
  ☆30Updated last year
• wyvernSemi / mem_model
  High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
  ☆24Updated 7 months ago
• tarik-ibrahimovic / eduBOS5
  A compact, configurable RISC-V core
  ☆11Updated 3 months ago
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆47Updated 7 months ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆70Updated 9 months ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆47Updated 2 years ago
• mattvenn / flipflop_demo
  Flip flop setup, hold & metastability explorer tool
  ☆34Updated 2 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆20Updated 2 years ago
• tmeissner / vhdl_verification
  Examples and design pattern for VHDL verification
  ☆15Updated 9 years ago
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆28Updated 2 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆49Updated 2 months ago
• VHDL / PoC
  IP Core Library - Published and maintained by the Open Source VHDL Group
  ☆14Updated this week
• AsFigo / apb_uvc_verilator
  APB UVC ported to Verilator
  ☆11Updated last year
• aignacio / nox
  RISC-V Nox core
  ☆64Updated 2 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated last year
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆71Updated this week
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆31Updated 8 months ago
• chili-chips-ba / openPCIE
  Peripheral Component Interconnect has taken Express lane long ago, going for xGbps SerDes. Now (for the first time) in opensource on the …
  ☆13Updated 3 weeks ago
• PeterMonsson / sv_waveterm
  ☆10Updated last year