A Python package for generating HDL wrappers and top modules for HDL sources
☆60Updated this week
Alternatives and similar repositories for topwrap
Users that are interested in topwrap are comparing it to the libraries listed below
Sorting:
- Raptor end-to-end FPGA Compiler and GUI☆96Dec 11, 2024Updated last year
- ☆33Feb 20, 2026Updated last week
- Raw image/video data analyzer☆48Jan 29, 2025Updated last year
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 4 years ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37May 4, 2024Updated last year
- Library of FPGA architectures☆30Jan 6, 2026Updated last month
- VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation deb…☆37Nov 6, 2025Updated 3 months ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- ☆14Oct 2, 2023Updated 2 years ago
- Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language☆17Feb 20, 2019Updated 7 years ago
- KISCV, a KISS principle riscv32i CPU☆28Jan 11, 2025Updated last year
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆27Feb 2, 2026Updated 3 weeks ago
- A tiny 3-stage RISC-V core written in Chisel.☆16Apr 14, 2023Updated 2 years ago
- GSI Timing Gateware and Tools☆14Feb 20, 2026Updated last week
- Fault Injection Automatic Test Equipment☆16Nov 22, 2021Updated 4 years ago
- ☆14Updated this week
- Open source Logic Analyzer based on LiteX SoC☆27Apr 12, 2025Updated 10 months ago
- A Python package to use FPGA development tools programmatically.☆144Mar 22, 2025Updated 11 months ago
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆32Oct 15, 2024Updated last year
- Conecting the Litefury FPGA accelerator to Raspberry Pi 5 over PCIe gen2 x1☆39Feb 18, 2024Updated 2 years ago
- ☆30Apr 1, 2017Updated 8 years ago
- Picorv32 SoC that uses only BRAM, not flash memory☆13Nov 27, 2018Updated 7 years ago
- Microarchitectural control flow integrity (𝜇CFI) verification checks whether there exists a control or data flow from instruction's ope…☆16Feb 12, 2026Updated 2 weeks ago
- Hardware Snappy decompressor☆11Sep 11, 2024Updated last year
- SGMII☆13Jul 17, 2014Updated 11 years ago
- Soft-logic designs and HAL libraries for various subsystems found in Oxide hardware.☆17Feb 18, 2026Updated last week
- Quickly update a bitstream with new RAM contents☆16Jun 8, 2021Updated 4 years ago
- Code for paper entitled "Low Cost FPGA based Implementation of a DRFM System"☆31Dec 10, 2021Updated 4 years ago
- SystemVerilog Linter based on pyslang☆31May 5, 2025Updated 9 months ago
- An open source, parameterized SystemVerilog digital hardware IP library☆33May 26, 2024Updated last year
- Generate Zynq configurations without using the vendor GUI☆30Jul 5, 2023Updated 2 years ago
- Opensource DDR3 Controller☆417Jan 18, 2026Updated last month
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆30Mar 29, 2013Updated 12 years ago
- IP Catalog for Raptor.☆17Dec 6, 2024Updated last year
- FPGA for uSDR☆20Updated this week
- VHDL code generator for AXI4-lite register files☆12May 22, 2024Updated last year
- Making Lattice SensAI work properly on tinyVision products☆12Nov 22, 2022Updated 3 years ago
- ☆18Feb 20, 2026Updated last week
- Generator for CRC HDL code (VHDL, Verilog, MyHDL)☆43Oct 13, 2023Updated 2 years ago