antmicro / topwrapLinks
A Python package for generating HDL wrappers and top modules for HDL sources
☆33Updated 2 weeks ago
Alternatives and similar repositories for topwrap
Users that are interested in topwrap are comparing it to the libraries listed below
Sorting:
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- A compact, configurable RISC-V core☆11Updated 2 months ago
- A padring generator for ASICs☆25Updated 2 years ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 6 months ago
- USB virtual model in C++ for Verilog☆30Updated 7 months ago
- ☆32Updated 4 months ago
- IP Core Library - Published and maintained by the Open Source VHDL Group☆12Updated last month
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆17Updated 2 months ago
- Generate Zynq configurations without using the vendor GUI☆30Updated last year
- SystemVerilog Linter based on pyslang☆30Updated 3 weeks ago
- Bitstream relocation and manipulation tool.☆46Updated 2 years ago
- ☆33Updated 2 years ago
- ☆36Updated 2 years ago
- Virtual development board for HDL design☆42Updated 2 years ago
- ☆26Updated last year
- Flip flop setup, hold & metastability explorer tool☆34Updated 2 years ago
- Docker Development Environment for SpinalHDL☆20Updated 9 months ago
- UART models for cocotb☆29Updated 2 years ago
- Peripheral Component Interconnect has taken Express lane long ago, going for xGbps SerDes. Now (for the first time) in opensource on the …☆11Updated this week
- An automatic clock gating utility☆48Updated last month
- Open source RTL simulation acceleration on commodity hardware☆27Updated 2 years ago
- ☆21Updated last month
- FPGA250 aboard the eFabless Caravel☆29Updated 4 years ago
- ☆22Updated this week
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆54Updated this week
- ☆59Updated 3 years ago
- Python interface to FPGA interchange format☆41Updated 2 years ago
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- Making cocotb testbenches that bit easier☆29Updated 2 months ago