Alternatives and similar repositories for vaporview

Users that are interested in vaporview are comparing it to the libraries listed below

• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆209Updated 6 months ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆127Updated 3 months ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆144Updated this week
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆45Updated 7 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆162Updated this week
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆384Updated 3 months ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆181Updated 2 weeks ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆156Updated 3 months ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆197Updated last week
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆137Updated last month
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆342Updated this week
• themperek / cocotb-test
  Unit testing for cocotb
  ☆162Updated this week
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆232Updated 2 weeks ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆156Updated 2 months ago
• rggen / rggen
  Code generation tool for control and status registers
  ☆422Updated last week
• AndrewNolte / vscode-system-verilog
  SystemVerilog/Verilog support for vscode
  ☆36Updated this week
• ZipCPU / sdspi
  SD-Card controller, using either SPI, SDIO, or eMMC interfaces
  ☆311Updated 4 months ago
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆76Updated 3 months ago
• wavedrom / vcdrom
  VCD viewer
  ☆94Updated 3 weeks ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆245Updated 11 months ago
• jeremiah-c-leary / vhdl-style-guide
  Style guide enforcement for VHDL
  ☆219Updated last week
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆116Updated last year
• librelane / librelane
  ASIC implementation flow infrastructure
  ☆115Updated this week
• efabless / openlane2
  The next generation of OpenLane, rewritten from scratch with a modular architecture
  ☆312Updated 6 months ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆110Updated last year
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 7 months ago
• raysalemi / Python4RTLVerification
  ☆166Updated 3 years ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆417Updated 2 weeks ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆65Updated last month
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆94Updated this week