Lramseyer / vaporviewLinks
Waveform Viewer Extension for VScode
☆281Updated this week
Alternatives and similar repositories for vaporview
Users that are interested in vaporview are comparing it to the libraries listed below
Sorting:
- SystemVerilog synthesis tool☆216Updated 7 months ago
 - Control and status register code generator toolchain☆150Updated 3 weeks ago
 - SystemVerilog frontend for Yosys☆168Updated this week
 - Control and Status Register map generator for HDL projects☆127Updated 5 months ago
 - Fabric generator and CAD tools.☆201Updated last week
 - A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆185Updated last week
 - Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆235Updated last month
 - Opensource DDR3 Controller☆389Updated 4 months ago
 - WAL enables programmable waveform analysis.☆160Updated last week
 - A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆147Updated last week
 - A demo system for Ibex including debug support and some peripherals☆78Updated 4 months ago
 - Standard Cell Library based Memory Compiler using FF/Latch cells☆160Updated 3 weeks ago
 - Code generation tool for control and status registers☆427Updated last month
 - Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆65Updated last month
 - Test suite designed to check compliance with the SystemVerilog standard.☆346Updated this week
 - The next generation of OpenLane, rewritten from scratch with a modular architecture☆316Updated 8 months ago
 - SystemVerilog/Verilog support for vscode☆36Updated last month
 - Verilog UART☆184Updated 12 years ago
 - Unit testing for cocotb☆163Updated last month
 - Python script to transform a VCD file to wavedrom format☆81Updated 3 years ago
 - ASIC implementation flow infrastructure☆148Updated this week
 - lowRISC Style Guides☆461Updated 4 months ago
 - Functional Coverage and Constrained Randomization Extensions for Cocotb☆117Updated last month
 - Style guide enforcement for VHDL☆225Updated 3 weeks ago
 - ☆166Updated 3 years ago
 - Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆113Updated last year
 - ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆98Updated last week
 - Experimental flows using nextpnr for Xilinx devices☆245Updated last year
 - SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆423Updated last month
 - A simple, basic, formally verified UART controller☆311Updated last year