Lramseyer / vaporviewLinks
Waveform Viewer Extension for VScode
☆292Updated this week
Alternatives and similar repositories for vaporview
Users that are interested in vaporview are comparing it to the libraries listed below
Sorting:
- SystemVerilog synthesis tool☆220Updated 9 months ago
- Control and status register code generator toolchain☆156Updated last week
- Control and Status Register map generator for HDL projects☆128Updated 6 months ago
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆192Updated last week
- SystemVerilog frontend for Yosys☆178Updated last week
- Opensource DDR3 Controller☆399Updated 6 months ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆169Updated this week
- Fabric generator and CAD tools.☆209Updated this week
- WAL enables programmable waveform analysis.☆163Updated last month
- ASIC implementation flow infrastructure, successor to OpenLane☆210Updated this week
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆70Updated 2 months ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆190Updated 2 weeks ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆162Updated last month
- lowRISC Style Guides☆470Updated last month
- Unit testing for cocotb☆165Updated last week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆238Updated 3 months ago
- Style guide enforcement for VHDL☆228Updated last month
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆143Updated 3 weeks ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆321Updated last week
- Code generation tool for control and status registers☆435Updated 2 weeks ago
- A simple, basic, formally verified UART controller☆318Updated last year
- Verilog UART☆186Updated 12 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆102Updated last week
- Experimental flows using nextpnr for Xilinx devices☆248Updated last year
- Test suite designed to check compliance with the SystemVerilog standard.☆351Updated this week
- A demo system for Ibex including debug support and some peripherals☆84Updated last month
- ☆170Updated 3 years ago
- Verilog digital signal processing components☆161Updated 3 years ago
- ☆301Updated last month
- SystemVerilog/Verilog support for vscode using Ctags☆37Updated 2 months ago