Alternatives and similar repositories for dang

Users that are interested in dang are comparing it to the libraries listed below

• mole99 / greyhound-ihp
  Greyhound on IHP SG13G2 0.13 μm BiCMOS process
  ☆80Updated last week
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆95Updated last year
• zeroasiccorp / umi
  Universal Memory Interface (UMI)
  ☆157Updated this week
• najaeda / naja
  Structural Netlist API (and more) for EDA post synthesis flow development
  ☆133Updated this week
• pieter3d / simview
  ☆91Updated 3 months ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆105Updated last year
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆215Updated last week
• os-fpga / FOEDAG
  Framework Open EDA Gui
  ☆73Updated last year
• fischermoseley / manta
  A configurable and approachable tool for FPGA debugging and rapid prototyping.
  ☆147Updated 2 weeks ago
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆36Updated 3 months ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• PyFPGA / pyfpga
  A Python package to use FPGA development tools programmatically.
  ☆143Updated 10 months ago
• getinstachip / vpm
  Verilog package manager written in Rust
  ☆144Updated last year
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆111Updated this week
• pulp-platform / cheshire-ihp130-o
  ☆58Updated 10 months ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆110Updated this week
• librelane / librelane
  ASIC implementation flow infrastructure, successor to OpenLane
  ☆276Updated this week
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆74Updated 4 months ago
• efabless / caravel_user_project_analog
  ☆51Updated last year
• hudson-trading / slang-server
  A SystemVerilog language server based on the Slang library.
  ☆113Updated last week
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆201Updated this week
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆120Updated 2 years ago
• vmunoz82 / sudoku-challenge
  Solving Sudokus using open source formal verification tools
  ☆18Updated 3 years ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated last year
• microsoft / cheriot-ibex
  cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
  ☆119Updated 5 months ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆164Updated 2 months ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆172Updated 2 months ago
• pulp-platform / carfield
  A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …
  ☆117Updated 6 months ago
• aignacio / nox
  RISC-V Nox core
  ☆71Updated 6 months ago
• VHDL / pyVHDLModel
  An abstract language model of VHDL written in Python.
  ☆60Updated last week