Alternatives and similar repositories for tree-sitter-systemverilog

Users that are interested in tree-sitter-systemverilog are comparing it to the libraries listed below

• vivekmalneedi / veridian
  A SystemVerilog Language Server
  ☆184Updated 6 months ago
• imc-trading / svlangserver
  ☆120Updated last year
• tree-sitter / tree-sitter-verilog
  SystemVerilog grammar for tree-sitter
  ☆108Updated 11 months ago
• dalance / svlint
  SystemVerilog linter
  ☆360Updated last month
• suoto / hdl_checker
  Repurposing existing HDL tools to help writing better code
  ☆217Updated last year
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆64Updated 9 months ago
• jpt13653903 / tree-sitter-vhdl
  A VHDL parser for syntax highlighting.
  ☆16Updated 3 weeks ago
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆142Updated 8 months ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆234Updated last month
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆156Updated 4 months ago
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆62Updated last year
• dalance / svls
  SystemVerilog language server
  ☆539Updated last week
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆344Updated this week
• suzizecat / slang-lsp-tools
  Tools based upon slang for language server purpose
  ☆17Updated 2 weeks ago
• sifferman / schematics
  Examples of how to Generate Schematics from SystemVerilog Synthesis Tools
  ☆22Updated last year
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆165Updated last week
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆228Updated last week
• intel / rohd-vf
  The ROHD Verification Framework is a hardware verification framework built upon ROHD for building testbenches.
  ☆45Updated last week
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆140Updated last year
• antmicro / sv-bugpoint
  ☆30Updated 3 weeks ago
• chipsalliance / homebrew-verible
  ☆22Updated 3 months ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆214Updated 7 months ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆127Updated 3 weeks ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆420Updated last month
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆451Updated 7 months ago
• ucsc-vama / essent
  high-performance RTL simulator
  ☆178Updated last year
• rameloni / tywaves-chisel
  A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…
  ☆49Updated 11 months ago
• n-kremeris / verilator_basics
  ☆68Updated 2 years ago
• AndrewNolte / vscode-system-verilog
  SystemVerilog/Verilog support for vscode
  ☆36Updated last month
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆327Updated last week