SystemVerilog tree-sitter grammar
☆57Jul 20, 2026Updated 3 weeks ago
Alternatives and similar repositories for tree-sitter-systemverilog
Users that are interested in tree-sitter-systemverilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog grammar for tree-sitter☆123Nov 11, 2024Updated last year
- tree-sitter grammar/parser for INI files☆35Dec 8, 2025Updated 8 months ago
- A SystemVerilog language server based on the Slang library.☆301Updated this week
- SystemVerilog compiler and language services☆1,115Updated this week
- smelt is a library to create, execute and analyze integration tests☆28Jun 2, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Generate address space documentation HTML from compiled SystemRDL input☆65Mar 6, 2026Updated 5 months ago
- csv grammar for tree-sitter☆12Nov 13, 2025Updated 9 months ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆35Apr 13, 2021Updated 5 years ago
- A SystemVerilog Language Server☆208Nov 30, 2025Updated 8 months ago
- Parse objdump files using tree-sitter☆13Nov 22, 2023Updated 2 years ago
- LD linker script grammar for tree-sitter☆11Nov 19, 2023Updated 2 years ago
- A command-line tool for displaying vcd waveforms.☆71Feb 19, 2024Updated 2 years ago
- A tool for modeling FSMs by VHDL or Verilog☆14Aug 3, 2026Updated 2 weeks ago
- Parse disassembly files using tree-sitter☆14Dec 3, 2023Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- SystemVerilog linter☆388Nov 6, 2025Updated 9 months ago
- Mirrors of the Accellera UVM Reference Implementations at https://www.accellera.org/downloads/standards/uvm.☆16Aug 23, 2021Updated 4 years ago
- ☆20May 5, 2020Updated 6 years ago
- ☆14Oct 30, 2024Updated last year
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,907Updated this week
- Verilog Extensions for Emacs☆67Jul 16, 2026Updated last month
- SV/DPI library allowing multiple simulations/platforms to run in parallel and communicate☆16Feb 24, 2026Updated 5 months ago
- A tool for analysing the source-level static connectivity of a SystemVerilog design☆25Jul 18, 2026Updated last month
- A simple Emacs minor mode for VUnit☆12Jul 14, 2025Updated last year
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆481Jun 10, 2026Updated 2 months ago
- SystemVerilog language server☆583Jul 28, 2026Updated 3 weeks ago
- Emacs Verilog Tree-sitter Major-mode☆12Jul 16, 2026Updated last month
- Verilog AST☆21Dec 2, 2023Updated 2 years ago
- VerilogAI – A specialized chatbot for Verilog. Supports code generation, debugging, and explanation with custom prompt engineering and AP…☆18Apr 26, 2026Updated 3 months ago
- Import and export IP-XACT XML register models☆39Nov 5, 2025Updated 9 months ago
- A hardware compiler based on LLHD and CIRCT☆271Jun 30, 2025Updated last year
- ☆14Dec 7, 2023Updated 2 years ago
- LLM Agent for Hardware Description Language☆23Jun 7, 2025Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Tree-sitter parser for .gitignore files☆26May 4, 2022Updated 4 years ago
- Common SystemVerilog RTL modules for RgGen☆16Feb 5, 2026Updated 6 months ago
- Python Tool for UVM Testbench Generation☆56May 19, 2024Updated 2 years ago
- SystemVerilog syntax highlight/indent support in vim☆52Jul 10, 2024Updated 2 years ago
- Tool for generating multi-purpose makefiles for FPGA projects (clone of hdlmake from CERN)☆18Aug 16, 2021Updated 5 years ago
- Perl 单行解释中文版☆12Dec 20, 2018Updated 7 years ago
- PSSGen: Portable Test and Stimulus Standard DSL Generator☆15Jun 30, 2026Updated last month