SystemVerilog tree-sitter grammar
☆58Jul 20, 2026Updated last month
Alternatives and similar repositories for tree-sitter-systemverilog
Users that are interested in tree-sitter-systemverilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog grammar for tree-sitter☆123Nov 11, 2024Updated last year
- tree-sitter grammar/parser for INI files☆35Dec 8, 2025Updated 9 months ago
- A SystemVerilog language server based on the Slang library.☆311Updated this week
- SystemVerilog compiler and language services☆1,132Updated this week
- smelt is a library to create, execute and analyze integration tests☆28Jun 2, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Generate address space documentation HTML from compiled SystemRDL input☆65Mar 6, 2026Updated 6 months ago
- csv grammar for tree-sitter☆12Nov 13, 2025Updated 9 months ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆35Apr 13, 2021Updated 5 years ago
- A SystemVerilog Language Server☆209Nov 30, 2025Updated 9 months ago
- Parse objdump files using tree-sitter☆13Nov 22, 2023Updated 2 years ago
- LD linker script grammar for tree-sitter☆11Nov 19, 2023Updated 2 years ago
- A command-line tool for displaying vcd waveforms.☆71Feb 19, 2024Updated 2 years ago
- Parse disassembly files using tree-sitter☆13Dec 3, 2023Updated 2 years ago
- ☆20May 5, 2020Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Mirrors of the Accellera UVM Reference Implementations at https://www.accellera.org/downloads/standards/uvm.☆18Aug 23, 2021Updated 5 years ago
- ☆14Oct 30, 2024Updated last year
- A VHDL parser for syntax highlighting.☆25Updated this week
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,931Updated this week
- SV/DPI library allowing multiple simulations/platforms to run in parallel and communicate☆16Feb 24, 2026Updated 6 months ago
- A tool for analysing the source-level static connectivity of a SystemVerilog design☆26Updated this week
- A simple Emacs minor mode for VUnit☆12Jul 14, 2025Updated last year
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆482Jun 10, 2026Updated 2 months ago
- SystemVerilog language server☆584Aug 25, 2026Updated 2 weeks ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Emacs Verilog Tree-sitter Major-mode☆12Jul 16, 2026Updated last month
- Verilog AST☆21Dec 2, 2023Updated 2 years ago
- VerilogAI – A specialized chatbot for Verilog. Supports code generation, debugging, and explanation with custom prompt engineering and AP…☆18Apr 26, 2026Updated 4 months ago
- Import and export IP-XACT XML register models☆39Nov 5, 2025Updated 10 months ago
- A suite of tools for pretty printing, diffing, and exploring abstract syntax trees.☆18Aug 11, 2026Updated 3 weeks ago
- A hardware compiler based on LLHD and CIRCT☆270Jun 30, 2025Updated last year
- ☆14Dec 7, 2023Updated 2 years ago
- ☆30Oct 2, 2023Updated 2 years ago
- LLM Agent for Hardware Description Language☆23Jun 7, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Tree-sitter parser for .gitignore files☆26May 4, 2022Updated 4 years ago
- Common SystemVerilog RTL modules for RgGen☆16Feb 5, 2026Updated 7 months ago
- Python Tool for UVM Testbench Generation☆56May 19, 2024Updated 2 years ago
- SystemVerilog syntax highlight/indent support in vim☆52Jul 10, 2024Updated 2 years ago
- ☆16Jul 15, 2026Updated last month
- Tool for generating multi-purpose makefiles for FPGA projects (clone of hdlmake from CERN)☆18Aug 16, 2021Updated 5 years ago
- PSSGen: Portable Test and Stimulus Standard DSL Generator☆15Jun 30, 2026Updated 2 months ago