gmlarumbe / tree-sitter-systemverilogLinks
SystemVerilog tree-sitter grammar
☆42Updated 2 months ago
Alternatives and similar repositories for tree-sitter-systemverilog
Users that are interested in tree-sitter-systemverilog are comparing it to the libraries listed below
Sorting:
- A SystemVerilog Language Server☆189Updated 3 weeks ago
- ☆127Updated last month
- SystemVerilog grammar for tree-sitter☆114Updated last year
- Python bindings for slang, a library for compiling SystemVerilog☆65Updated 11 months ago
- Repurposing existing HDL tools to help writing better code☆219Updated last year
- SystemVerilog linter☆371Updated last month
- A command-line tool for displaying vcd waveforms.☆65Updated last year
- A VHDL parser for syntax highlighting.☆18Updated last week
- SystemVerilog language server☆554Updated last week
- WAL enables programmable waveform analysis.☆163Updated last month
- Tools based upon slang for language server purpose☆20Updated last week
- SystemVerilog frontend for Yosys☆184Updated this week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆238Updated 3 months ago
- SystemVerilog support in VS Code☆145Updated 10 months ago
- Test suite designed to check compliance with the SystemVerilog standard.☆352Updated this week
- A SystemVerilog language server based on the Slang library.☆91Updated this week
- Examples of how to Generate Schematics from SystemVerilog Synthesis Tools☆22Updated 2 years ago
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆55Updated last year
- Python packages providing a library for Verification Stimulus and Coverage☆134Updated last month
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆144Updated last year
- A tool for synthesizing Verilog programs☆108Updated 4 months ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆430Updated 3 months ago
- high-performance RTL simulator☆184Updated last year
- A Fast, Low-Overhead On-chip Network☆255Updated last week
- A dependency management tool for hardware projects.☆338Updated last week
- Create WaveJSON from VCD file. WaveDrom can convert it to timing diagram.☆40Updated last year
- A dynamic verification library for Chisel.☆159Updated last year
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆232Updated this week
- SystemVerilog/Verilog support for vscode using Ctags☆37Updated 3 months ago
- SystemVerilog synthesis tool☆220Updated 9 months ago