Alternatives and similar repositories for tree-sitter-systemverilog

Users that are interested in tree-sitter-systemverilog are comparing it to the libraries listed below

• imc-trading / svlangserver
  ☆109Updated 11 months ago
• tree-sitter / tree-sitter-verilog
  SystemVerilog grammar for tree-sitter
  ☆99Updated 6 months ago
• sifferman / schematics
  Examples of how to Generate Schematics from SystemVerilog Synthesis Tools
  ☆22Updated last year
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆58Updated 3 months ago
• vivekmalneedi / veridian
  A SystemVerilog Language Server
  ☆168Updated last month
• n-kremeris / verilator_basics
  ☆62Updated 2 years ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆132Updated last year
• antmicro / sv-bugpoint
  ☆26Updated 3 weeks ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆83Updated last year
• suzizecat / slang-lsp-tools
  Tools based upon slang for language server purpose
  ☆12Updated last month
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆56Updated last year
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆149Updated 2 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆103Updated this week
• rameloni / tywaves-chisel
  A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…
  ☆41Updated 6 months ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆120Updated this week
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆150Updated 6 months ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆137Updated this week
• accellera / uvm
  ☆51Updated 9 years ago
• openformal / sva_basics
  This repository is compilation of basics of System Verilog Assertions in context of formal verification
  ☆20Updated 6 years ago
• gmlarumbe / verilog-ext
  Verilog Extensions for Emacs
  ☆61Updated last month
• ucsc-vama / essent
  high-performance RTL simulator
  ☆158Updated 10 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆201Updated this week
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆59Updated last year
• Kuree / hgdb
  Hardware generator debugger
  ☆73Updated last year
• cclienti / svmodule
  SystemVerilog & Verilog Module I/O parser and printer
  ☆25Updated 3 years ago
• chipsalliance / uvm-verilator
  ☆92Updated last year
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆136Updated 2 months ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆196Updated last week
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆78Updated this week
• esl-epfl / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆180Updated this week