Alternatives and similar repositories for tree-sitter-systemverilog:

Users that are interested in tree-sitter-systemverilog are comparing it to the libraries listed below

• imc-trading / svlangserver
  ☆109Updated 10 months ago
• tree-sitter / tree-sitter-verilog
  SystemVerilog grammar for tree-sitter
  ☆98Updated 4 months ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆55Updated 2 months ago
• vivekmalneedi / veridian
  A SystemVerilog Language Server
  ☆157Updated 3 months ago
• gmlarumbe / verilog-ext
  Verilog Extensions for Emacs
  ☆62Updated 2 weeks ago
• n-kremeris / verilator_basics
  ☆61Updated 2 years ago
• sifferman / schematics
  Examples of how to Generate Schematics from SystemVerilog Synthesis Tools
  ☆22Updated last year
• suoto / hdl_checker
  Repurposing existing HDL tools to help writing better code
  ☆204Updated 9 months ago
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆137Updated last month
• chipsalliance / uvm-verilator
  ☆89Updated last year
• antoinemadec / vim-verilog-instance
  verilog_instance.vim: create instantiation of ports from port declaration
  ☆27Updated 2 years ago
• antoinemadec / uvm_code_gen
  Simple template-based UVM code generator
  ☆24Updated 2 years ago
• antmicro / sv-bugpoint
  ☆25Updated 3 weeks ago
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆53Updated last year
• rameloni / tywaves-chisel
  A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…
  ☆40Updated 5 months ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆127Updated last year
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆69Updated last week
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆147Updated 4 months ago
• accellera / uvm
  ☆49Updated 8 years ago
• openformal / sva_basics
  This repository is compilation of basics of System Verilog Assertions in context of formal verification
  ☆20Updated 6 years ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆120Updated 3 weeks ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆185Updated this week
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆81Updated 2 weeks ago
• nanamake / vcd2json
  Create WaveJSON from VCD file. WaveDrom can convert it to timing diagram.
  ☆35Updated 8 months ago
• cclienti / svmodule
  SystemVerilog & Verilog Module I/O parser and printer
  ☆25Updated 3 years ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆80Updated last year
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆130Updated 3 weeks ago
• chipsalliance / homebrew-verible
  ☆18Updated last month
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆147Updated last month
• intel / rohd-vf
  The ROHD Verification Framework is a hardware verification framework built upon ROHD for building testbenches.
  ☆41Updated 2 months ago