Alternatives and similar repositories for tree-sitter-systemverilog

Users that are interested in tree-sitter-systemverilog are comparing it to the libraries listed below

• tree-sitter / tree-sitter-verilog
  SystemVerilog grammar for tree-sitter
  ☆113Updated last year
• imc-trading / svlangserver
  ☆129Updated 2 months ago
• vivekmalneedi / veridian
  A SystemVerilog Language Server
  ☆195Updated last month
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆65Updated last year
• suoto / hdl_checker
  Repurposing existing HDL tools to help writing better code
  ☆222Updated last year
• dalance / svlint
  SystemVerilog linter
  ☆373Updated 2 months ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆163Updated 2 months ago
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆146Updated 11 months ago
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆65Updated last year
• nanamake / vcd2json
  Create WaveJSON from VCD file. WaveDrom can convert it to timing diagram.
  ☆40Updated last year
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆187Updated last week
• ucsc-vama / essent
  high-performance RTL simulator
  ☆185Updated last year
• hudson-trading / slang-server
  A SystemVerilog language server based on the Slang library.
  ☆104Updated this week
• rameloni / tywaves-chisel
  A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…
  ☆55Updated last year
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆108Updated 4 months ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆243Updated 4 months ago
• jpt13653903 / tree-sitter-vhdl
  A VHDL parser for syntax highlighting.
  ☆21Updated last week
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆135Updated 2 months ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆176Updated 2 weeks ago
• AndrewNolte / vscode-system-verilog
  SystemVerilog/Verilog support for vscode using Ctags
  ☆37Updated 4 months ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆159Updated last year
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆225Updated 10 months ago
• antmicro / sv-bugpoint
  ☆34Updated 3 weeks ago
• raczben / fliplot
  HTML & Js based VCD viewer
  ☆66Updated last week
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆356Updated this week
• sifferman / schematics
  Examples of how to Generate Schematics from SystemVerilog Synthesis Tools
  ☆22Updated 2 years ago
• chipsalliance / uvm-verilator
  ☆113Updated 2 months ago
• suzizecat / slang-lsp-tools
  Tools based upon slang for language server purpose
  ☆20Updated 2 weeks ago
• accellera-official / uvm-core
  ☆109Updated last year
• pulp-platform / snitch_cluster
  An energy-efficient RISC-V floating-point compute cluster.
  ☆121Updated this week