Alternatives and similar repositories for pyslint

Users that are interested in pyslint are comparing it to the libraries listed below

• themperek / spicebind
  SpiceBind – spice inside HDL simulator
  ☆56Updated 3 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆76Updated 3 months ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆43Updated 2 years ago
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆36Updated 3 weeks ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆37Updated last week
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆70Updated 4 months ago
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆35Updated last month
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• antmicro / verilator-verification
  Test dashboard for verification features in Verilator
  ☆27Updated this week
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆71Updated last week
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆47Updated last year
• rggen / rggen-sv-rtl
  Common SystemVerilog RTL modules for RgGen
  ☆13Updated last month
• oddball / ipxact2systemverilog
  Translates IPXACT XML to synthesizable VHDL or SystemVerilog
  ☆63Updated last week
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆39Updated last week
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆62Updated 4 years ago
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆29Updated last year
• mohamed / fsm2sv
  SystemVerilog FSM generator
  ☆32Updated last year
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆57Updated last month
• schang412 / cocotbext-spi
  ☆26Updated 6 months ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆81Updated 3 years ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆54Updated last year
• pulp-platform / svase
  ☆32Updated 9 months ago
• SymbiFlow / sphinx-verilog-domain
  Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.
  ☆25Updated 4 years ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆30Updated 2 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆50Updated 6 months ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆54Updated 5 years ago
• wallento / cocotbext-uart
  UART cocotb module
  ☆11Updated 4 years ago
• dh73 / A_Formal_Tale_Chapter_I_AMBA
  AXI Formal Verification IP
  ☆20Updated 4 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆50Updated last year