Kuree / fsim
Fiber-based SystemVerilog Simulator.
☆25Updated 2 years ago
Alternatives and similar repositories for fsim:
Users that are interested in fsim are comparing it to the libraries listed below
- Experiments with Yosys cxxrtl backend☆47Updated this week
- Hardware generator debugger☆73Updated 11 months ago
- GDB server to debug CPU simulation waveform traces☆42Updated 2 years ago
- A Verilog Synthesis Regression Test☆35Updated 9 months ago
- User-friendly explanation of Yosys options☆112Updated 3 years ago
- 👾 Design ∪ Hardware☆72Updated 2 months ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆27Updated last month
- Exploring gate level simulation☆56Updated 2 years ago
- Testing processors with Random Instruction Generation☆30Updated last week
- RISC-V Processor written in Amaranth HDL☆35Updated 2 years ago
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆42Updated 2 weeks ago
- Instrumenting adders to measure speed☆13Updated 2 years ago
- USB virtual model in C++ for Verilog☆28Updated 3 months ago
- PicoRV☆44Updated 4 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆19Updated 3 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- ☆33Updated 2 years ago
- Naive Educational RISC-V -- A simple single-stage RV32I processor☆25Updated 4 years ago
- Debuggable hardware generator☆67Updated last year
- Next-Generation FPGA Place-and-Route☆10Updated 6 years ago
- ☆52Updated 2 years ago
- Benchmarks for Yosys development☆23Updated 4 years ago
- Mutation Cover with Yosys (MCY)☆78Updated last month
- A SystemVerilog source file pickler.☆53Updated 2 months ago
- SystemVerilog frontend for Yosys☆68Updated last week
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆25Updated this week
- A padring generator for ASICs☆24Updated last year
- SoftCPU/SoC engine-V☆54Updated last year
- System on Chip toolkit for Amaranth HDL☆85Updated 3 months ago
- Naive Educational RISC V processor☆77Updated 3 months ago