ash-aldujaili / spatial-filter-hdlLinks
High Throughput Image Filters on FPGAs
☆14Updated 8 years ago
Alternatives and similar repositories for spatial-filter-hdl
Users that are interested in spatial-filter-hdl are comparing it to the libraries listed below
Sorting:
- A Direct Memory Access Controller (DMAC) with AHB-lite bus interface☆15Updated last year
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Updated 10 years ago
- ☆34Updated 2 years ago
- Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).☆62Updated 3 years ago
- Reconfigurable Binary Engine☆17Updated 4 years ago
- IP operations in verilog (simulation and implementation on ice40)☆61Updated 6 years ago
- HW and SW based implementation of Canny Edge Detection Algorithm.☆12Updated 7 years ago
- ☆46Updated 5 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆19Updated 7 years ago
- Theia: ray graphic processing unit☆20Updated 11 years ago
- We are aimed at making a device for shooting real-time HDR (High Dynamic Range) video using FPGA.☆32Updated 6 years ago
- double_fpu_verilog☆18Updated 11 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆66Updated 8 years ago
- A multi-board Extended Kalman Filter (EKF)☆32Updated 7 years ago
- Express DLA implementation for FPGA, revised based on NVDLA.☆11Updated 6 years ago
- ASIC Design of the openSPARC Floating Point Unit☆14Updated 8 years ago
- Verilog Implementation of the Census Transform Stereo Vision algorithm☆29Updated 2 years ago
- MIPI CSI-2 RX☆37Updated 4 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Updated 5 months ago
- Register-based and RAM-based FIFOs designed in Verilog/System Verilog.☆19Updated last year
- Demonstration of a video processing design for the Digilent Zybo, using Web Camera for input and VGA interface for output.☆25Updated 9 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 5 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆50Updated 9 years ago
- ☆40Updated last year
- A configurable general purpose graphics processing unit for☆11Updated 6 years ago
- HOG + SVM on FPGA☆27Updated 4 years ago
- Basic floating-point components for RISC-V processors☆10Updated 8 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- RTL implementation of TFlite FPGA accelerator and RISC-V controller. 3D Object Detection based on LiDAR Point Clouds.☆13Updated 2 years ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆27Updated 2 weeks ago