Alternatives and similar repositories for spatial-filter-hdl

Users that are interested in spatial-filter-hdl are comparing it to the libraries listed below

• edwardclin2003 / LowPassFilterImageFPGA
  Verilog code that does 2D Low Pass Filter on a greyscale image
  ☆10Updated 10 years ago
• shalan / MS_DMAC_AHBL
  A Direct Memory Access Controller (DMAC) with AHB-lite bus interface
  ☆15Updated last year
• hellgate202 / csi2_rx
  MIPI CSI-2 RX
  ☆37Updated 3 years ago
• cornell-zhang / facedetect-fpga
  ☆46Updated 5 years ago
• slongfield / StereoCensus
  Verilog Implementation of the Census Transform Stereo Vision algorithm
  ☆29Updated 2 years ago
• pulp-platform / rbe
  Reconfigurable Binary Engine
  ☆17Updated 4 years ago
• andrewandrepowell / zybo_petalinux_video_hls
  Demonstration of a video processing design for the Digilent Zybo, using Web Camera for input and VGA interface for output.
  ☆25Updated 9 years ago
• jm2000 / RISCV-FPU
  Basic floating-point components for RISC-V processors
  ☆10Updated 8 years ago
• freecores / double_fpu
  double_fpu_verilog
  ☆16Updated 11 years ago
• freecores / theia_gpu
  Theia: ray graphic processing unit
  ☆20Updated 11 years ago
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆16Updated 5 years ago
• jomonkjoy / Tool-Make-Script
  Synopsys Design compiler, VCS and Tetra-MAX
  ☆19Updated 7 years ago
• damdoy / fpga_image_processing
  IP operations in verilog (simulation and implementation on ice40)
  ☆60Updated 5 years ago
• sh-vlad / FPGA_rtime_HDR_video
  We are aimed at making a device for shooting real-time HDR (High Dynamic Range) video using FPGA.
  ☆32Updated 6 years ago
• PacoReinaCampo / SoC-RISCV
  System on Chip with RISCV-32 / RISCV-64 / RISCV-128
  ☆22Updated 4 months ago
• deepaktabraham / FPGA-Acceleration-of-Canny-Edge-Detection-Algorithm
  HW and SW based implementation of Canny Edge Detection Algorithm.
  ☆12Updated 7 years ago
• SeanZarzycki / openSPARC-FPU
  ASIC Design of the openSPARC Floating Point Unit
  ☆14Updated 8 years ago
• unihd-cag / openhmc
  openHMC - an open source Hybrid Memory Cube Controller
  ☆50Updated 9 years ago
• shehanmunasinghe / tinyGPU
  tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog
  ☆51Updated 4 years ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆31Updated 9 years ago
• g0kul / vcnn
  Verilog Convolutional Neural Network on PYNQ
  ☆28Updated 7 years ago
• pulp-platform / neureka
  2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters
  ☆27Updated 2 weeks ago
• verilator / example-systemverilog
  ☆40Updated last year
• freecores / video_stream_scaler
  Video Stream Scaler
  ☆40Updated 11 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆67Updated 7 months ago
• jdocampom / JPEG-Decoder
  Verilog Code for a JPEG Decoder
  ☆34Updated 7 years ago
• SameLight / ITRI-OpenDLA
  Express DLA implementation for FPGA, revised based on NVDLA.
  ☆10Updated 5 years ago
• ahegazy / vlsi-notes
  Digital IC design and vlsi notes
  ☆12Updated 5 years ago
• iammituraj / FIFOs
  Register-based and RAM-based FIFOs designed in Verilog/System Verilog.
  ☆19Updated last year
• pulp-platform / pulp-dsp
  ☆35Updated 2 years ago