hengfengzhang / soc
soc integration script and integration smoke script
☆21Updated 2 years ago
Alternatives and similar repositories for soc:
Users that are interested in soc are comparing it to the libraries listed below
- System Verilog and Emulation. Written all the five channels.☆32Updated 7 years ago
- UVM register utility generation by inputting xls table☆35Updated last year
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆30Updated 2 years ago
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆33Updated 4 years ago
- AHB-APB UVM Verification Environment☆17Updated 9 years ago
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆66Updated 5 years ago
- UVM resource from github, run simulation use YASAsim flow☆27Updated 4 years ago
- This is the repository for the IEEE version of the book☆56Updated 4 years ago
- UVM Generator☆44Updated 9 months ago
- UVM Testbench For SystemVerilog Combinator Implementation☆53Updated 8 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆16Updated 10 years ago
- JSON lib in Systemverilog☆42Updated 2 years ago
- Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence☆29Updated 4 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆43Updated 11 months ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆24Updated 2 years ago
- UVM APB VIP, part of AMBA3&AMBA4 feature supported☆31Updated 4 years ago
- Verification IP for APB protocol☆57Updated 4 years ago
- ☆35Updated 9 years ago
- ☆24Updated 3 years ago
- UVM VIP architecture generator☆19Updated 4 years ago
- UVM examples☆10Updated 9 years ago
- Sample UVM code for axi ram dut☆30Updated 3 years ago
- ☆12Updated 9 years ago
- ☆36Updated last year
- DOULOS Easier UVM Code Generator☆31Updated 7 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆19Updated 12 years ago
- 支持AXI总线协议的8k×8 SP SRAM☆25Updated 4 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆73Updated 6 years ago
- AXI Interconnect☆47Updated 3 years ago
- Download proccedings from DVCon☆22Updated 3 years ago