hengfengzhang / socView external linksLinks
soc integration script and integration smoke script
☆24Sep 12, 2022Updated 3 years ago
Alternatives and similar repositories for soc
Users that are interested in soc are comparing it to the libraries listed below
Sorting:
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- ☆16Apr 21, 2019Updated 6 years ago
- Various low power labs using sky130☆13Sep 3, 2021Updated 4 years ago
- ☆20Aug 22, 2022Updated 3 years ago
- CNN accelerator using NoC architecture☆17Dec 6, 2018Updated 7 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆65Jan 13, 2021Updated 5 years ago
- ☆18Aug 11, 2022Updated 3 years ago
- Generate a Verilog Source file and testbench file for a given Moore FSM☆17Nov 18, 2012Updated 13 years ago
- UVM candy lover testbench which uses YASA as simulation script☆17Apr 17, 2020Updated 5 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- Collection of IPs based on AMBA (AHB, APB, AXI) protocols☆19Feb 1, 2017Updated 9 years ago
- Yet Another Simulation Architecture☆79Sep 17, 2020Updated 5 years ago
- A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS☆34Oct 23, 2025Updated 3 months ago
- Verilog-Based-NoC-Simulator☆10May 4, 2016Updated 9 years ago
- Small and simple, primitive SoC with GPU, CPU, RAM, GPIO☆14Dec 29, 2016Updated 9 years ago
- Medium Access Control layer of 802.15.4☆13Nov 14, 2014Updated 11 years ago
- ☆11Mar 10, 2023Updated 2 years ago
- ☆12Nov 11, 2015Updated 10 years ago
- 标准视频时序生成器☆10Feb 9, 2020Updated 6 years ago
- RISC-V CPU in SystemVerilog & Custom Migen-based SoC Generator☆10Dec 29, 2021Updated 4 years ago
- Project of an integrated UART: RTL, Verification, Physical Implementation (Innovus) and GDSII.☆16May 28, 2021Updated 4 years ago
- 位宽和深度可定制的异步FIFO☆13May 29, 2024Updated last year
- Generic AHB master stub☆12Jul 17, 2014Updated 11 years ago
- 第四届全国大学生嵌入式比赛SoC☆11Apr 1, 2022Updated 3 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- A simple spidergon network-on-chip with wormhole switching feature☆12Mar 22, 2021Updated 4 years ago
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆74Nov 22, 2019Updated 6 years ago
- Direct Access Memory for MPSoC☆13Jan 27, 2026Updated 2 weeks ago
- DMA core compatible with AHB3-Lite☆10Mar 30, 2019Updated 6 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- ☆16May 10, 2019Updated 6 years ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- ☆14Feb 24, 2025Updated 11 months ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 6 years ago
- UVM testbench for verifying the Pulpino SoC☆13Mar 23, 2020Updated 5 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Nov 9, 2015Updated 10 years ago
- Verification of Ethernet Switch System Verilog☆11Oct 21, 2016Updated 9 years ago
- amba3 apb/axi vip☆53Feb 24, 2015Updated 10 years ago
- Contains commonly used UVM components (agents, environments and tests).☆32Aug 17, 2018Updated 7 years ago