rhysd / riscv32-cpu-chiselLinks
Learning how to make RISC-V 32bit CPU with Chisel
☆67Updated 3 years ago
Alternatives and similar repositories for riscv32-cpu-chisel
Users that are interested in riscv32-cpu-chisel are comparing it to the libraries listed below
Sorting:
- Wrapper for Rocket-Chip on FPGAs☆134Updated 2 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆51Updated 2 years ago
- Run rocket-chip on FPGA☆68Updated 6 months ago
- Chisel examples and code snippets☆251Updated 2 years ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆198Updated 2 months ago
- ☆67Updated 3 months ago
- Provides various testers for chisel users☆100Updated 2 years ago
- ☆66Updated 9 months ago
- A Chisel RTL generator for network-on-chip interconnects☆198Updated 3 weeks ago
- Modern co-simulation framework for RISC-V CPUs☆145Updated this week
- ☆86Updated last month
- Unit tests generator for RVV 1.0☆85Updated 3 weeks ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆94Updated 2 weeks ago
- riscv32i-cpu☆18Updated 4 years ago
- ☆64Updated last month
- chipyard in mill :P☆78Updated last year
- Open-source high-performance non-blocking cache☆82Updated last week
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆231Updated 9 months ago
- A teaching-focused RISC-V CPU design used at UC Davis☆147Updated 2 years ago
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆48Updated last year
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆55Updated last year
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- A dynamic verification library for Chisel.☆151Updated 6 months ago
- An almost empty chisel project as a starting point for hardware design☆31Updated 4 months ago
- A RISC-V Core (RV32I) written in Chisel HDL☆102Updated 2 months ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆40Updated last year
- ☆18Updated 2 years ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆94Updated 2 months ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆154Updated last year
- a training-target implementation of rv32im, designed to be simple and easy to understand☆59Updated 3 years ago