Learning how to make RISC-V 32bit CPU with Chisel
☆70Sep 17, 2021Updated 4 years ago
Alternatives and similar repositories for riscv32-cpu-chisel
Users that are interested in riscv32-cpu-chisel are comparing it to the libraries listed below
Sorting:
- ☆236Mar 20, 2023Updated 2 years ago
- riscv32i-cpu☆18Nov 20, 2020Updated 5 years ago
- Chisel3 AXI4-{Lite, Full, Stream} Definitions☆15Dec 31, 2018Updated 7 years ago
- Simple RISC-V 3-stage Pipeline in Chisel☆604Aug 9, 2024Updated last year
- A RISC-V Core (RV32I) written in Chisel HDL☆107Feb 3, 2026Updated last month
- Digital Design with Chisel☆898Updated this week
- Lab3: Construct a single-cycle CPU with Chisel☆18Nov 20, 2023Updated 2 years ago
- A Tiny Processor Core☆114Jul 14, 2025Updated 7 months ago
- An almost empty chisel project as a starting point for hardware design☆35Jan 27, 2025Updated last year
- Support Repository of "How to make RISC-V Microcomputer using FPGA for programmer"☆18Jul 30, 2019Updated 6 years ago
- Write a CPU from scratch! (5-stage pipeline & 2-way-cache)☆20Jul 18, 2019Updated 6 years ago
- A template project for beginning new Chisel work☆692Feb 24, 2026Updated last week
- 大三上做的本科毕设，包含BNN的替代梯度训练，verilog电路实现，完成180nm工艺流片。☆21Jun 30, 2025Updated 8 months ago
- Density test bench for RISCV - "Compress extension"☆15Jun 21, 2021Updated 4 years ago
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,113Sep 10, 2024Updated last year
- A template for developing custom FIRRTL transforms☆10Jan 30, 2020Updated 6 years ago
- 🕹 Implementation for the lesson Compiling Engineering(2020 Spring) in Peking University, adjusted from UCLA CS 132 Project.☆10Jun 21, 2020Updated 5 years ago
- ☆10May 16, 2021Updated 4 years ago
- Verilog RTL Implementation of DNN☆10Jun 26, 2018Updated 7 years ago
- Chaitin-Briggs register-allocation algorithm (LLVM back-end)☆12Jan 6, 2016Updated 10 years ago
- Provides various testers for chisel users☆101Jan 12, 2023Updated 3 years ago
- ☆12Sep 18, 2024Updated last year
- RISC-V Zve32x, Zve32f, Zvfh Vector Coprocessor☆16Feb 17, 2026Updated 2 weeks ago
- Iodine: Verifying Constant-Time Execution of Hardware☆15Mar 29, 2021Updated 4 years ago
- RTL code for the DPU chip designed for irregular graphs☆13May 30, 2022Updated 3 years ago
- ☆12May 8, 2025Updated 9 months ago
- ☆13May 5, 2023Updated 2 years ago
- ☆10Dec 15, 2023Updated 2 years ago
- Paper list for accleration of transformers☆14Jul 1, 2023Updated 2 years ago
- ☆12Mar 11, 2021Updated 4 years ago
- Instruction Pointer Classifier and Dynamic Degree Stream based Hardware Cache Prefetching☆16Nov 16, 2019Updated 6 years ago
- ☆10Dec 28, 2020Updated 5 years ago
- Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.☆18Feb 3, 2026Updated last month
- A verilog implementation for Network-on-Chip☆81Feb 3, 2018Updated 8 years ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆234Jan 14, 2026Updated last month
- Examples for creating AXI-interfaced peripherals in Chisel☆75Nov 15, 2015Updated 10 years ago
- Chisel examples and code snippets☆268Aug 1, 2022Updated 3 years ago
- A Chisel RTL generator for network-on-chip interconnects☆226Nov 7, 2025Updated 3 months ago
- ☆14Jun 16, 2021Updated 4 years ago