Alternatives and similar repositories for riscv32-cpu-chisel

Users that are interested in riscv32-cpu-chisel are comparing it to the libraries listed below

• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 2 years ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆81Updated 3 weeks ago
• OSCPU / ysyxSoC
  ☆86Updated last week
• riscv-and-rust-and-decaf / riscv32i-cpu-chisel
  riscv32i-cpu
  ☆18Updated 4 years ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆84Updated last month
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆39Updated last year
• OSCPU / chisel-playground
  ☆67Updated 3 months ago
• OSCPU / yosys-sta
  ☆63Updated 3 weeks ago
• THU-DSP-LAB / ventus-gpgpu-verilog
  GPGPU supporting RISCV-V, developed with verilog HDL
  ☆98Updated 2 months ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆133Updated 2 years ago
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆52Updated 5 years ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆150Updated 6 months ago
• OpenXiangShan / xs-env
  XiangShan Frontend Develop Environment
  ☆56Updated this week
• CherrySprings / CherrySprings
  ☆18Updated 2 years ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆49Updated this week
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆196Updated this week
• ysyx-ta / ysyx-summer-readings
  ☆66Updated 9 months ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated 11 months ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆142Updated this week
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆92Updated this week
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆250Updated 2 years ago
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆114Updated 5 months ago
• Jpz-sdju / trinity
  ☆20Updated last month
• OpenXiangShan / GEM5
  ☆84Updated this week
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆156Updated 6 months ago
• schoeberl / chisel-empty
  An almost empty chisel project as a starting point for hardware design
  ☆30Updated 3 months ago
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆142Updated 3 months ago
• chipsalliance / playground
  chipyard in mill :P
  ☆78Updated last year
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆70Updated last year
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆177Updated 3 weeks ago