Alternatives and similar repositories for riscv32-cpu-chisel

Users that are interested in riscv32-cpu-chisel are comparing it to the libraries listed below

• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆265Updated 3 years ago
• jlpteaching / dinocpu
  A teaching-focused RISC-V CPU design used at UC Davis
  ☆153Updated 2 years ago
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆118Updated 2 months ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆221Updated 2 months ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆171Updated this week
• OpenXiangShan / xs-env
  XiangShan Frontend Develop Environment
  ☆68Updated this week
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆107Updated 2 months ago
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆53Updated 5 years ago
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆77Updated 2 months ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆138Updated 3 years ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆77Updated this week
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆110Updated 4 months ago
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆60Updated 2 years ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆54Updated 3 years ago
• schoeberl / chisel-empty
  An almost empty chisel project as a starting point for hardware design
  ☆33Updated last year
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated 3 years ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆92Updated last month
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆163Updated 2 years ago
• riscv-and-rust-and-decaf / riscv32i-cpu-chisel
  riscv32i-cpu
  ☆18Updated 5 years ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆160Updated last year
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆194Updated 4 months ago
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆161Updated 11 months ago
• leros-dev / leros
  A Tiny Processor Core
  ☆114Updated 6 months ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆225Updated 2 months ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆111Updated 2 years ago
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆114Updated 2 years ago
• Jpz-sdju / trinity
  ☆32Updated 6 months ago
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆233Updated last year
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆100Updated 2 months ago