rhysd / riscv32-cpu-chiselLinks
Learning how to make RISC-V 32bit CPU with Chisel
☆70Updated 4 years ago
Alternatives and similar repositories for riscv32-cpu-chisel
Users that are interested in riscv32-cpu-chisel are comparing it to the libraries listed below
Sorting:
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆107Updated 2 months ago
- A teaching-focused RISC-V CPU design used at UC Davis☆150Updated 2 years ago
- Wrapper for Rocket-Chip on FPGAs☆138Updated 3 years ago
- A RISC-V Core (RV32I) written in Chisel HDL☆105Updated last month
- Chisel examples and code snippets☆263Updated 3 years ago
- XiangShan Frontend Develop Environment☆68Updated 2 weeks ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Updated 3 years ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆217Updated last month
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆59Updated 2 years ago
- Unit tests generator for RVV 1.0☆98Updated last month
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆112Updated last month
- Run rocket-chip on FPGA☆76Updated last month
- Pick your favorite language to verify your chip.☆73Updated 2 weeks ago
- ☆69Updated 2 years ago
- Modern co-simulation framework for RISC-V CPUs☆165Updated this week
- An almost empty chisel project as a starting point for hardware design☆33Updated 10 months ago
- Chisel Learning Journey☆111Updated 2 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆159Updated last year
- A matrix extension proposal for AI applications under RISC-V architecture☆156Updated 10 months ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- ☆32Updated 4 months ago
- Provides various testers for chisel users☆100Updated 2 years ago
- A dynamic verification library for Chisel.☆159Updated last year
- Open-source high-performance non-blocking cache☆92Updated 2 weeks ago
- riscv32i-cpu☆18Updated 5 years ago
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆53Updated 5 years ago
- Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor☆46Updated last month
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆191Updated 2 weeks ago
- A Tiny Processor Core☆114Updated 5 months ago