Angelic47 / GowinDDR3_AXI4_SpinalHDL
Gowin DDR3 Controller with AXI4 Implementation | 高云DDR3内存控制器AXI4接口实现
☆21Updated 11 months ago
Alternatives and similar repositories for GowinDDR3_AXI4_SpinalHDL:
Users that are interested in GowinDDR3_AXI4_SpinalHDL are comparing it to the libraries listed below
- SPI-Flash XIP Interface (Verilog)☆36Updated 3 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆58Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆62Updated 4 years ago
- An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆45Updated 7 months ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆48Updated last year
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆30Updated 4 years ago
- Must-have verilog systemverilog modules☆30Updated 2 years ago
- ☆28Updated 5 years ago
- USB 2.0 Device IP Core☆59Updated 7 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆18Updated 5 years ago
- AHB DMA 32 / 64 bits☆52Updated 10 years ago
- ☆53Updated 2 years ago
- All digital PLL☆27Updated 7 years ago
- FPGA Technology Exchange Group相关文件管理☆43Updated last year
- RTL Verilog library for various DSP modules☆84Updated 3 years ago
- SDRAM controller with AXI4 interface☆87Updated 5 years ago
- ☆23Updated 2 years ago
- Verilog Ethernet Switch (layer 2)☆40Updated last year
- UART -> AXI Bridge☆60Updated 3 years ago
- ☆24Updated 3 years ago
- FPGA和USB3.0桥片实现USB3.0通信☆60Updated 3 years ago
- Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核☆21Updated 2 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆41Updated last year
- ☆16Updated 5 years ago
- Bitmap Processing Library & AXI-Stream Video Image VIP☆30Updated 2 years ago
- IP operations in verilog (simulation and implementation on ice40)☆55Updated 5 years ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆16Updated 3 years ago
- xkDLA:XinKai Deep Learning Accelerator (RTL)☆28Updated last year