ultraembedded / core_uriscv
Another tiny RISC-V implementation
☆51Updated 3 years ago
Related projects: ⓘ
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆69Updated 5 months ago
- Wishbone interconnect utilities☆34Updated 3 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆57Updated 5 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆54Updated this week
- Basic USB 1.1 Host Controller for small FPGAs☆84Updated 4 years ago
- Yet Another RISC-V Implementation☆82Updated 8 months ago
- RISCV model for Verilator/FPGA targets☆44Updated 4 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆72Updated last year
- USB Full Speed PHY☆38Updated 4 years ago
- Minimal DVI / HDMI Framebuffer☆74Updated 4 years ago
- Reusable Verilog 2005 components for FPGA designs☆34Updated last year
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆78Updated 4 years ago
- IEEE 754 floating point library in system-verilog and vhdl☆26Updated 4 months ago
- Featherweight RISC-V implementation☆52Updated 2 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆63Updated 2 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆55Updated last year
- JTAG Test Access Port (TAP)☆30Updated 10 years ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆41Updated this week
- ☆56Updated 3 years ago
- turbo 8051☆28Updated 7 years ago
- A small 32-bit implementation of the RISC-V architecture☆31Updated 4 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆58Updated last year
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆86Updated 3 years ago
- Ethernet MAC 10/100 Mbps☆75Updated 4 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆29Updated 3 years ago
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆27Updated 3 months ago
- A simple DDR3 memory controller☆49Updated last year
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- Platform Level Interrupt Controller☆34Updated 4 months ago
- Naive Educational RISC V processor☆69Updated last year