ultraembedded / core_uriscvLinks
Another tiny RISC-V implementation
☆64Updated 4 years ago
Alternatives and similar repositories for core_uriscv
Users that are interested in core_uriscv are comparing it to the libraries listed below
Sorting:
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆101Updated last month
- Minimal DVI / HDMI Framebuffer☆83Updated 5 years ago
- Yet Another RISC-V Implementation☆99Updated last year
- SoftCPU/SoC engine-V☆55Updated 10 months ago
- Basic USB 1.1 Host Controller for small FPGAs☆97Updated 5 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆72Updated 7 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆86Updated last year
- Demo SoC for SiliconCompiler.☆62Updated this week
- Verilog implementation of a RISC-V core☆134Updated 7 years ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆108Updated 4 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆71Updated 3 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆83Updated 5 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆82Updated 3 years ago
- Featherweight RISC-V implementation☆53Updated 4 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆81Updated 6 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆127Updated 6 months ago
- A set of Wishbone Controlled SPI Flash Controllers☆97Updated 3 years ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆77Updated this week
- ☆60Updated 4 years ago
- Wishbone interconnect utilities☆44Updated last month
- A small 32-bit implementation of the RISC-V architecture☆32Updated 5 years ago
- JTAG Test Access Port (TAP)☆37Updated 11 years ago
- 3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.☆92Updated 5 years ago
- Spen's Official OpenOCD Mirror☆51Updated 10 months ago
- This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…☆91Updated 5 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆53Updated last year
- SpinalHDL Hardware Math Library☆94Updated last year
- USB 2.0 FS Device controller IP core written in SystemVerilog☆39Updated 7 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆39Updated last month