Alternatives and similar repositories for core_uriscv

Users that are interested in core_uriscv are comparing it to the libraries listed below

• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated 6 months ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 7 months ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆101Updated 4 years ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆95Updated this week
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆95Updated 5 years ago
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆82Updated 5 years ago
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆80Updated last year
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆53Updated 5 years ago
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆81Updated 5 years ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆74Updated 2 years ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆61Updated this week
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆97Updated last year
• risclite / ARM9-compatible-soft-CPU-core
  This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…
  ☆90Updated 4 years ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆46Updated 7 months ago
• olgirard / openmsp430
  The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
  ☆65Updated 7 years ago
• rbarzic / nanorv32
  A small 32-bit implementation of the RISC-V architecture
  ☆32Updated 5 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆78Updated 2 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆121Updated 2 months ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆69Updated 3 years ago
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆80Updated 5 years ago
• aignacio / mpsoc_example
  ☆61Updated 4 years ago
• zxmarcos / huedeon-gpu
  FPGA GPU design for DE1-SoC
  ☆74Updated 3 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆89Updated 2 years ago
• ultraembedded / core_ftdi_bridge
  FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge
  ☆33Updated 4 years ago
• freecores / jtag
  JTAG Test Access Port (TAP)
  ☆36Updated 11 years ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆53Updated 3 years ago
• damdoy / fpga_image_processing
  IP operations in verilog (simulation and implementation on ice40)
  ☆60Updated 5 years ago
• Kenji-Ishimaru / polyphony
  3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.
  ☆90Updated 5 years ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆125Updated 6 years ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆51Updated 11 months ago