Alternatives and similar repositories for core_uriscv

Users that are interested in core_uriscv are comparing it to the libraries listed below

• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆94Updated this week
• olgirard / openmsp430
  The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
  ☆65Updated 7 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 7 months ago
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆83Updated 5 years ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆53Updated 5 years ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆93Updated 5 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆97Updated 11 months ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated 5 months ago
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆80Updated 5 years ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆60Updated last week
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆101Updated 3 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆38Updated 3 years ago
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆80Updated last year
• aignacio / mpsoc_example
  ☆61Updated 4 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆34Updated 7 months ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆74Updated 2 years ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆124Updated 6 years ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆46Updated 6 months ago
• rbarzic / nanorv32
  A small 32-bit implementation of the RISC-V architecture
  ☆32Updated 5 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆69Updated 3 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆88Updated 2 years ago
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆81Updated 5 years ago
• esynr3z / usb20dev
  USB 2.0 FS Device controller IP core written in SystemVerilog
  ☆36Updated 6 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆77Updated 2 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆119Updated 2 months ago
• zxmarcos / huedeon-gpu
  FPGA GPU design for DE1-SoC
  ☆74Updated 3 years ago
• Dmitriy0111 / nanoFOX
  A small RISC-V core (SystemVerilog)
  ☆32Updated 6 years ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆53Updated 3 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆84Updated 5 years ago
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆109Updated last year