ultraembedded / core_uriscv
Another tiny RISC-V implementation
☆54Updated 3 years ago
Alternatives and similar repositories for core_uriscv:
Users that are interested in core_uriscv are comparing it to the libraries listed below
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆61Updated 4 years ago
- Yet Another RISC-V Implementation☆86Updated 4 months ago
- Minimal DVI / HDMI Framebuffer☆79Updated 4 years ago
- RISCV model for Verilator/FPGA targets☆49Updated 5 years ago
- Wishbone interconnect utilities☆38Updated last week
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆73Updated this week
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆74Updated 10 months ago
- JTAG Test Access Port (TAP)☆32Updated 10 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆64Updated 2 years ago
- SoftCPU/SoC engine-V☆54Updated last year
- Basic USB 1.1 Host Controller for small FPGAs☆88Updated 4 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆67Updated 10 months ago
- Embedded 32-bit RISC uProcessor with SDRAM Controller☆25Updated 3 years ago
- Hamming ECC Encoder and Decoder to protect memories☆29Updated 2 weeks ago
- Generic FIFO implementation with optional FWFT☆55Updated 4 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆79Updated 2 years ago
- ☆59Updated 3 years ago
- USB -> AXI Debug Bridge☆35Updated 3 years ago
- turbo 8051☆28Updated 7 years ago
- IP operations in verilog (simulation and implementation on ice40)☆55Updated 5 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆78Updated 5 years ago
- I2C controller core☆38Updated 2 years ago
- USB Full Speed PHY☆39Updated 4 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆65Updated 2 years ago
- Extensible FPGA control platform☆57Updated last year
- FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge☆32Updated 3 years ago
- Wishbone controlled I2C controllers☆45Updated 3 months ago
- Experiments with fixed function renderers and Chisel HDL☆59Updated 5 years ago
- Reusable Verilog 2005 components for FPGA designs☆40Updated last year