Alternatives and similar repositories for core_uriscv:

Users that are interested in core_uriscv are comparing it to the libraries listed below

• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆63Updated 4 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆39Updated last month
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆41Updated 4 years ago
• freecores / jtag
  JTAG Test Access Port (TAP)
  ☆33Updated 10 years ago
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆76Updated 11 months ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆89Updated 5 months ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆49Updated 5 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆31Updated last month
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆88Updated 4 years ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆57Updated last week
• aignacio / mpsoc_example
  ☆59Updated 3 years ago
• ultraembedded / core_ftdi_bridge
  FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge
  ☆32Updated 3 years ago
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆29Updated 2 months ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆79Updated 2 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆36Updated 10 months ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆44Updated 4 months ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆69Updated 2 years ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆66Updated 2 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆63Updated last month
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆79Updated 5 years ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆94Updated 3 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last year
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆68Updated 2 years ago
• rbarzic / nanorv32
  A small 32-bit implementation of the RISC-V architecture
  ☆32Updated 4 years ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆79Updated 5 months ago
• viktor-nikolov / MicroBlaze-DDR3-tutorial
  Tutorial of a HW design of MicroBlaze using DDR3 RAM on Arty A7 board; DDR3 RAM speed test application
  ☆44Updated 9 months ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆37Updated 3 years ago
• freecores / usbhostslave
  USB 1.1 Host and Function IP core
  ☆21Updated 10 years ago
• ChrisPVille / jtaglet
  Easy-to-use JTAG TAP and Debug Controller core written in Verilog
  ☆27Updated 6 years ago
• openhwgroup / cve2
  The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…
  ☆37Updated this week