Another tiny RISC-V implementation
☆64Jul 19, 2021Updated 4 years ago
Alternatives and similar repositories for core_uriscv
Users that are interested in core_uriscv are comparing it to the libraries listed below
Sorting:
- A reconfigurable logic circuit made of identical rotatable tiles.☆24Nov 15, 2021Updated 4 years ago
- 32-bit Superscalar RISC-V CPU☆1,197Sep 18, 2021Updated 4 years ago
- USB capture IP☆25Jun 6, 2020Updated 5 years ago
- FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge☆32Jun 5, 2021Updated 4 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆45Sep 21, 2022Updated 3 years ago
- AVR CPU Core Implementation in Verilog HDL.☆14Oct 28, 2018Updated 7 years ago
- Support Repository of "How to make RISC-V Microcomputer using FPGA for programmer"☆18Jul 30, 2019Updated 6 years ago
- Yet Another Debug Transport☆25Dec 3, 2025Updated 3 months ago
- ☆15Jan 8, 2023Updated 3 years ago
- Verilator open-source SystemVerilog simulator and lint system☆23Updated this week
- RISC-V CPU Core (RV32IM)☆1,668Sep 18, 2021Updated 4 years ago
- This is just a senior project for now, but I wish for this to become a free, open source software for anyone and everyone to use!☆13Apr 26, 2022Updated 3 years ago
- Y80e - Z80/Z180 compatible processor extended by eZ80 instructions☆21Jul 17, 2014Updated 11 years ago
- fpga for utrasound mobile device☆13Aug 10, 2015Updated 10 years ago
- New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi…☆107Aug 28, 2025Updated 6 months ago
- Verilog CAN controller that is compatible to the SJA 1000.☆16Apr 17, 2021Updated 4 years ago
- ☆16Jan 12, 2021Updated 5 years ago
- A cheap iCE40 development board, designed on and for Raspberry Pi☆29Jul 7, 2019Updated 6 years ago
- Verilog VPI VGA Simulator using SDL☆11Feb 9, 2015Updated 11 years ago
- Zet - The x86 (IA-32) open implementation☆23Jul 17, 2014Updated 11 years ago
- This is a collection of the built in libraries of the VHDPlus IDE toghether with examples. Commits will be featured in the IDE with futur…☆20Feb 27, 2024Updated 2 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Jan 6, 2022Updated 4 years ago
- Example of how to use UVM with Verilator☆39Feb 19, 2026Updated last month
- A very simple SDRAM controller for FPGA written in Verilog. It exposes a SRAM-like interface to the rest of the FPGA fabric☆14Dec 4, 2018Updated 7 years ago
- GPGPU-Sim provides a detailed simulation model of a contemporary GPU running CUDA and/or OpenCL workloads and now includes an integrated…☆14Jun 24, 2020Updated 5 years ago
- Unnamed Compiled Systems Language Project☆25Nov 9, 2023Updated 2 years ago
- Amber ARM-compatible core☆16Jul 17, 2014Updated 11 years ago
- Latest in the line of the E32 processors with better/generic cache placement☆10Feb 25, 2023Updated 3 years ago
- MBLANC: mini Board Lab and Companion☆11Jan 5, 2023Updated 3 years ago
- USB -> AXI Debug Bridge☆43Jun 5, 2021Updated 4 years ago
- Basic RISC-V Test SoC☆180Apr 7, 2019Updated 6 years ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Feb 23, 2026Updated 3 weeks ago
- Software Emulation Library for the RP2040 Interpolator peripheral☆14Oct 25, 2025Updated 4 months ago
- PLEASE MOVE TO PAWSv2☆16Feb 2, 2022Updated 4 years ago
- Quickly update a bitstream with new RAM contents☆16Jun 8, 2021Updated 4 years ago
- 🍁🍂🍃 A C# implementation of the 65el02 CPU.☆10Oct 12, 2021Updated 4 years ago
- Python GUI for UrJTAG library.☆22Mar 6, 2026Updated 2 weeks ago
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆61Jan 7, 2026Updated 2 months ago