lingscale / cc01
☆31Updated last month
Alternatives and similar repositories for cc01:
Users that are interested in cc01 are comparing it to the libraries listed below
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆55Updated last year
- ☆36Updated 6 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆38Updated 2 years ago
- ☆32Updated 3 weeks ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆38Updated last year
- Setup scripts and files needed to compile CoreMark on RISC-V☆65Updated 8 months ago
- Pure digital components of a UCIe controller☆59Updated last week
- ☆65Updated 2 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆61Updated last year
- ☆64Updated 2 years ago
- Open source high performance IEEE-754 floating unit☆68Updated last year
- ☆22Updated 2 years ago
- OpenXuantie - OpenE906 Core☆138Updated 9 months ago
- ☆54Updated 4 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆52Updated 8 months ago
- ☆43Updated 6 years ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆61Updated 2 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 4 years ago
- The Ultra-Low Power RISC Core☆15Updated 4 years ago
- Run rocket-chip on FPGA☆67Updated 5 months ago
- a training-target implementation of rv32im, designed to be simple and easy to understand☆57Updated 3 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆51Updated 5 years ago
- Platform Level Interrupt Controller☆39Updated 11 months ago
- Chisel Learning Journey☆108Updated 2 years ago
- Tests for example Rocket Custom Coprocessors☆73Updated 5 years ago
- zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this pro…☆36Updated 3 years ago
- Provides various testers for chisel users☆100Updated 2 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆52Updated 3 years ago
- SDRAM controller with AXI4 interface☆89Updated 5 years ago