☆30Mar 13, 2025Updated last year
Alternatives and similar repositories for cc01
Users that are interested in cc01 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ZC RISCV CORE☆12Dec 19, 2019Updated 6 years ago
- A configurable general purpose graphics processing unit for☆12May 18, 2019Updated 7 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 6 years ago
- Chisel Examples for the iCESugar FPGA Board☆12May 4, 2021Updated 5 years ago
- zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this pro…☆39Sep 21, 2021Updated 4 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- A PicoRV32 SoC for the TinyFPGA BX with peripherals designed for building games☆14Nov 2, 2018Updated 7 years ago
- A MATLAB function library containing encoders, decoders and weight enumerators for Reed-Muller codes.☆12Aug 19, 2023Updated 2 years ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 6 years ago
- Hybrid Memory Cube Simulation & Research Infrastructure☆17Jun 9, 2025Updated 11 months ago
- Ventus GPGPU ISA Simulator Based on Spike☆51Updated this week
- coffeescript based hardware description language☆14Jan 14, 2022Updated 4 years ago
- ☆21Aug 23, 2021Updated 4 years ago
- ☆11Apr 15, 2024Updated 2 years ago
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆23Aug 10, 2018Updated 7 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- ☆10Nov 12, 2019Updated 6 years ago
- Support Repository of "How to make RISC-V Microcomputer using FPGA for programmer"☆18Jul 30, 2019Updated 6 years ago
- CNN accelerator using NoC architecture☆18Dec 6, 2018Updated 7 years ago
- Final Project for Digital Systems Design Course, Fall 2020☆17Jul 20, 2022Updated 3 years ago
- Theia: ray graphic processing unit☆20Jul 17, 2014Updated 11 years ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆20Updated this week
- QO100 UHF-VHF-HF UP/DOW Frequency-Converter☆21Jun 17, 2020Updated 5 years ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆27Jan 11, 2019Updated 7 years ago
- Craft a toy compiler☆10Aug 21, 2019Updated 6 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆25Sep 12, 2021Updated 4 years ago
- ☆15Sep 27, 2022Updated 3 years ago
- LUT LDPC is a collection of software tools to design and test LDPC decoders based on discrete message passing decoding using lookup table…☆16May 30, 2018Updated 7 years ago
- RiVer Core is an open source Python based RISC-V Core Verification framework.☆23Jun 16, 2025Updated 11 months ago
- centos 7 / ubuntu搭建torjan,公眾號:swa_yo☆12Feb 15, 2020Updated 6 years ago
- Polar coding, decoding, and testing☆13Oct 11, 2023Updated 2 years ago
- Fault Injection Automatic Test Equipment☆15Nov 22, 2021Updated 4 years ago
- A list Viterbo algorithm for decoding PAC codes with various code constructions/rate-profiles☆11May 6, 2022Updated 4 years ago
- ☆28Nov 15, 2019Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- UCSD CSE231 Advanced Compiler - LLVM project☆12Mar 28, 2017Updated 9 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Nov 21, 2019Updated 6 years ago
- ☆61Aug 30, 2021Updated 4 years ago
- Simple RISC-V 3-stage Pipeline in Chisel☆610Aug 9, 2024Updated last year
- Hardware and software implementation of Sparsely-active SNNs☆22Mar 6, 2026Updated 2 months ago
- RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.☆10Dec 11, 2020Updated 5 years ago
- Decoding of LDPC Codes Using the Information Bottleneck Method in Python☆17Dec 11, 2018Updated 7 years ago