☆30Mar 13, 2025Updated 11 months ago
Alternatives and similar repositories for cc01
Users that are interested in cc01 are comparing it to the libraries listed below
Sorting:
- ZC RISCV CORE☆12Dec 19, 2019Updated 6 years ago
- Ventus GPGPU ISA Simulator Based on Spike☆48Dec 28, 2025Updated 2 months ago
- Digital IC design and vlsi notes☆13Jun 24, 2020Updated 5 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 6 years ago
- coffeescript based hardware description language☆14Jan 14, 2022Updated 4 years ago
- Chisel Examples for the iCESugar FPGA Board☆12May 4, 2021Updated 4 years ago
- Final Project for Digital Systems Design Course, Fall 2020☆17Jul 20, 2022Updated 3 years ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 6 years ago
- A configurable general purpose graphics processing unit for☆12May 18, 2019Updated 6 years ago
- A PicoRV32 SoC for the TinyFPGA BX with peripherals designed for building games☆14Nov 2, 2018Updated 7 years ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆18Nov 12, 2025Updated 3 months ago
- zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this pro…☆39Sep 21, 2021Updated 4 years ago
- Hardware and software implementation of Sparsely-active SNNs☆22Feb 10, 2026Updated 2 weeks ago
- CNN accelerator using NoC architecture☆18Dec 6, 2018Updated 7 years ago
- This is an open CNN accelerator for everyone to use☆14Jul 15, 2019Updated 6 years ago
- ☆15Sep 27, 2022Updated 3 years ago
- Hybrid Memory Cube Simulation & Research Infrastructure☆17Jun 9, 2025Updated 8 months ago
- QO100 UHF-VHF-HF UP/DOW Frequency-Converter☆20Jun 17, 2020Updated 5 years ago
- RiVer Core is an open source Python based RISC-V Core Verification framework.☆23Jun 16, 2025Updated 8 months ago
- Support Repository of "How to make RISC-V Microcomputer using FPGA for programmer"☆18Jul 30, 2019Updated 6 years ago
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆23Aug 10, 2018Updated 7 years ago
- ☆21Aug 23, 2021Updated 4 years ago
- Biweekly Sync Meeting for RISC-V Software Ecosystem. Meeting time is more friendly for people living in East Asia.☆23Jan 24, 2026Updated last month
- Theia: ray graphic processing unit☆20Jul 17, 2014Updated 11 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Nov 21, 2019Updated 6 years ago
- ☆25Sep 12, 2021Updated 4 years ago
- uvm_axi is a uvm package for modeling and verifying AXI protocol☆21Feb 7, 2025Updated last year
- Network on Chip for MPSoC☆28Jan 27, 2026Updated last month
- tpu-systolic-array-weight-stationary☆25May 7, 2021Updated 4 years ago
- A Toy-Purpose TPU Simulator☆21Jun 7, 2024Updated last year
- Chisel implementation of Neural Processing Unit for System on the Chip☆26Jan 19, 2026Updated last month
- ☆60Aug 30, 2021Updated 4 years ago
- Public release☆58Sep 3, 2019Updated 6 years ago
- ☆29Oct 20, 2019Updated 6 years ago
- ☆28Nov 15, 2019Updated 6 years ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆26Jan 11, 2019Updated 7 years ago
- LIS Network-on-Chip Implementation☆34Aug 29, 2016Updated 9 years ago
- ☆31Aug 8, 2020Updated 5 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆14Mar 26, 2024Updated last year