lingscale / cc01Links
☆31Updated 3 months ago
Alternatives and similar repositories for cc01
Users that are interested in cc01 are comparing it to the libraries listed below
Sorting:
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆42Updated 2 years ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆41Updated last year
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago
- Open source high performance IEEE-754 floating unit☆75Updated last year
- ☆33Updated 3 months ago
- Pure digital components of a UCIe controller☆63Updated this week
- ☆59Updated 4 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆68Updated 11 months ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆62Updated last year
- ☆64Updated 2 years ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆55Updated last year
- ☆36Updated 6 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆54Updated 4 years ago
- ☆66Updated 3 years ago
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆24Updated 8 years ago
- ☆29Updated 4 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆64Updated last month
- Platform Level Interrupt Controller☆41Updated last year
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated 10 months ago
- DDR4 Simulation Project in System Verilog☆41Updated 10 years ago
- Open-source high-performance non-blocking cache☆83Updated 3 weeks ago
- RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…☆16Updated last year
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆18Updated last month
- Chisel Learning Journey☆109Updated 2 years ago
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆39Updated 2 years ago
- DEPRECATED. Please use Chipyard (https://github.com/ucb-bar/chipyard) to build BOOM☆36Updated 5 years ago
- General Purpose AXI Direct Memory Access☆51Updated last year
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago