lingscale / cc01
☆31Updated last year
Related projects ⓘ
Alternatives and complementary repositories for cc01
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆35Updated 2 years ago
- Basic floating-point components for RISC-V processors☆64Updated 4 years ago
- ☆75Updated 2 years ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆36Updated last year
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆56Updated 10 months ago
- Open source high performance IEEE-754 floating unit☆60Updated 8 months ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆93Updated this week
- ☆31Updated last month
- ☆64Updated 2 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆64Updated 4 months ago
- ☆25Updated 4 years ago
- SDRAM controller with AXI4 interface☆78Updated 5 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆69Updated 6 years ago
- ☆35Updated 6 years ago
- ☆48Updated 3 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆52Updated 4 years ago
- For contributions of Chisel IP to the chisel community.☆56Updated 2 weeks ago
- Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy☆41Updated 8 years ago
- Generic FIFO implementation with optional FWFT☆54Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆48Updated 5 months ago
- A Style Guide for the Chisel Hardware Construction Language☆106Updated 3 years ago
- The Ultra-Low Power RISC Core☆15Updated 4 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆47Updated 2 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆62Updated 5 months ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆58Updated 4 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆43Updated 2 years ago
- General Purpose AXI Direct Memory Access☆44Updated 6 months ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆57Updated last year
- Tests for example Rocket Custom Coprocessors☆69Updated 4 years ago
- a training-target implementation of rv32im, designed to be simple and easy to understand☆55Updated 2 years ago