DfX-NYUAD / TrojanSAINTLinks
TrojanSAINT: Gate-Level Netlist Sampling-Based Inductive Learning for Hardware Trojan Detection
☆12Updated last year
Alternatives and similar repositories for TrojanSAINT
Users that are interested in TrojanSAINT are comparing it to the libraries listed below
Sorting:
- A basic implementation of a SAT attack on logic locking.☆12Updated 3 years ago
- Must-read papers on Graph Neural Networks (GNNs) for Integrated Circuits (ICs) design, security and reliability.☆54Updated 2 months ago
- GNN-RE datasets for circuit recognition☆46Updated 2 years ago
- Optimal gate sizing of digital circuits using geometric programming☆11Updated 8 years ago
- Collection of digital hardware modules & projects (benchmarks)☆59Updated last month
- ☆31Updated 3 years ago
- Graph Neural Networks for Predicting Circuit Reliability Degradation. TCAD 2022☆20Updated 2 years ago
- Layout Symmetry Annotation for Analog Circuits with GraphNeural Networks☆14Updated 2 years ago
- Analog IC symmetry extraction benchmark of AncstrGNN☆10Updated 9 months ago
- This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download…☆25Updated 2 years ago
- ☆44Updated last year
- Artificial Netlist Generator☆39Updated last year
- ☆24Updated last year
- High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing☆51Updated last year
- ☆44Updated this week
- This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".☆21Updated last year
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆27Updated 5 years ago
- Re-host of ISCAS89 sequential benchmark circuits in higher level verilog (without "DFF")☆14Updated 3 years ago
- Benchmarks for Approximate Circuit Synthesis☆16Updated 4 years ago
- Circuit release of the MAGICAL project☆34Updated 5 years ago
- ☆15Updated 3 years ago
- ☆16Updated 4 years ago
- DATC RDF☆50Updated 4 years ago
- ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino☆54Updated 3 weeks ago
- ☆29Updated last year
- Delay Calculation ToolKit☆31Updated 2 years ago
- DATC Robust Design Flow.☆37Updated 5 years ago
- ☆17Updated 10 months ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆48Updated 4 months ago
- A collection of design automation algorithms, methodologies, and tools for electronics/photonics, and emerging eda technologies☆17Updated 2 years ago