Alternatives and similar repositories for TrojanSAINT

Users that are interested in TrojanSAINT are comparing it to the libraries listed below

• DfX-NYUAD / GNN-RE
  GNN-RE datasets for circuit recognition
  ☆56Updated 2 years ago
• cure-lab / DeepGate
  This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".
  ☆24Updated 2 years ago
• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆55Updated last year
• cure-lab / DeepGate2
  ☆16Updated 2 years ago
• SJTU-ECTL / ALSRAC
  ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set
  ☆21Updated last year
• Yu-Maryland / Verilog-to-PyG
  ☆30Updated last year
• lydiawunan / LOSTIN
  LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models
  ☆26Updated 3 years ago
• JBlocklove / LLMs-for-EDA-Tutorial
  ☆59Updated last week
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆79Updated last month
• scale-lab / BACS
  Benchmarks for Approximate Circuit Synthesis
  ☆17Updated 5 years ago
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆20Updated last month
• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆46Updated last year
• NYU-MLDA / OpenABC
  OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…
  ☆141Updated 6 months ago
• zshi0616 / DeepGate2
  ☆31Updated 2 years ago
• cad-polito-it / I99T
  ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino
  ☆67Updated 8 months ago
• DfX-NYUAD / GNN4IC
  Must-read papers on Graph Neural Networks (GNNs) for Integrated Circuits (ICs) design, security and reliability.
  ☆75Updated 6 months ago
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆61Updated last year
• CODA-Team / AncstrGNN_benchmark
  Analog IC symmetry extraction benchmark of AncstrGNN
  ☆10Updated last year
• lrakai / gate-sizing
  Optimal gate sizing of digital circuits using geometric programming
  ☆11Updated 9 years ago
• OSCC-Project / iMap
  Logic optimization and technology mapping tool.
  ☆20Updated 2 years ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆66Updated 8 months ago
• nputikhin / sat_atpg
  SAT-based ATPG using TG-Pro model
  ☆19Updated 7 years ago
• HKUST-GZ-VLSI / Design-Dataset
  This is a repo to store circuit design datasets
  ☆19Updated 2 years ago
• Chenghao-Yang / awesome-ml4ls
  Awesome machine learning for logic synthesis
  ☆30Updated 3 years ago
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆29Updated 6 years ago
• TimingPredict / TimingPredict
  Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)
  ☆88Updated last year
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆97Updated 2 months ago
• hkust-zhiyao / CircuitFusion
  CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)
  ☆32Updated 9 months ago
• bluesceada / iscas89_hl_verilog
  Re-host of ISCAS89 sequential benchmark circuits in higher level verilog (without "DFF")
  ☆15Updated 4 years ago
• zshi0616 / python-deepgate
  ☆27Updated last year