PeterLau61 / DeepRTLLinks
The official implementation of DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Model (ICLR 2025)
☆16Updated last month
Alternatives and similar repositories for DeepRTL
Users that are interested in DeepRTL are comparing it to the libraries listed below
Sorting:
- An open-source benchmark for generating design RTL with natural language☆155Updated last year
- Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)☆59Updated last year
- ☆65Updated 9 months ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆82Updated 2 months ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆66Updated 8 months ago
- This is a python repo for flattening Verilog☆20Updated last month
- Generative Benchmark for LLM-Aided Hardware Design☆26Updated 8 months ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆62Updated last month
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆76Updated 6 years ago
- ☆73Updated 7 years ago
- ☆46Updated last year
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆250Updated last year
- tpu-systolic-array-weight-stationary☆25Updated 4 years ago
- FSA: Fusing FlashAttention within a Single Systolic Array☆86Updated 5 months ago
- eyeriss-chisel3☆40Updated 3 years ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆50Updated last year
- HLS for Networks-on-Chip☆39Updated 4 years ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆91Updated 9 months ago
- Xilinx AXI VIP example of use☆43Updated 4 years ago
- This github repository summarizes relevant papers for shift left techniques in electronic design automation (EDA).☆30Updated 4 months ago
- This is a verilog implementation of 4x4 systolic array multiplier☆77Updated 5 years ago
- ☆40Updated 6 years ago
- ☆59Updated 3 weeks ago
- ☆109Updated 11 months ago
- ☆18Updated 4 years ago
- ☆58Updated 6 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆104Updated 3 weeks ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆84Updated 4 years ago
- The open-sourced version of BOOM-Explorer☆45Updated 2 years ago
- An AXI4 crossbar implementation in SystemVerilog☆208Updated 5 months ago