groupsada / DeepBurningLinks
Automatic generation of FPGA-based learning accelerators for the neural network family
☆66Updated 5 years ago
Alternatives and similar repositories for DeepBurning
Users that are interested in DeepBurning are comparing it to the libraries listed below
Sorting:
- RTL implementation of Flex-DPE.☆115Updated 5 years ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆159Updated this week
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆153Updated 5 months ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆91Updated last year
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆70Updated 3 weeks ago
- ☆72Updated 2 years ago
- ☆71Updated 5 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆230Updated 2 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.☆175Updated 3 months ago
- STONNE: A Simulation Tool for Neural Networks Engines☆145Updated 5 months ago
- Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…☆117Updated 5 months ago
- Exercises for exploring the Fibertree, Timeloop and Accelergy tools☆107Updated 7 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆82Updated 4 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 4 months ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆204Updated 5 years ago
- SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin☆113Updated 2 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆95Updated 4 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 3 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆74Updated last year
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆41Updated 4 years ago
- An FPGA Accelerator for Transformer Inference☆92Updated 3 years ago
- HLS implemented systolic array structure☆41Updated 8 years ago
- A DSL for Systolic Arrays☆82Updated 6 years ago
- Library of approximate arithmetic circuits☆58Updated 3 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆49Updated 8 months ago
- ☆71Updated 6 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆60Updated 3 years ago