Automatic generation of FPGA-based learning accelerators for the neural network family
☆68Dec 26, 2019Updated 6 years ago
Alternatives and similar repositories for DeepBurning
Users that are interested in DeepBurning are comparing it to the libraries listed below
Sorting:
- [FPGA-2022] N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores☆11Dec 16, 2021Updated 4 years ago
- ☆32Mar 31, 2025Updated 10 months ago
- ☆71Mar 22, 2020Updated 5 years ago
- ☆49Dec 10, 2024Updated last year
- Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.☆226Apr 22, 2019Updated 6 years ago
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆43Mar 30, 2021Updated 4 years ago
- Express DLA implementation for FPGA, revised based on NVDLA.☆11Oct 17, 2019Updated 6 years ago
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆13May 26, 2016Updated 9 years ago
- HLS project modeling various sparse accelerators.☆12Jan 11, 2022Updated 4 years ago
- Graph accelerator on FPGAs and ASICs☆11Aug 16, 2018Updated 7 years ago
- FPGA acceleration of arbitrary precision floating point computations.☆40May 17, 2022Updated 3 years ago
- mRNA☆26Mar 16, 2021Updated 4 years ago
- A general framework for optimizing DNN dataflow on systolic array☆39Jan 2, 2021Updated 5 years ago
- An open-sourced PyTorch library for developing energy efficient multiplication-less models and applications.☆14Feb 3, 2025Updated last year
- [ICML 2021] "Auto-NBA: Efficient and Effective Search Over the Joint Space of Networks, Bitwidths, and Accelerators" by Yonggan Fu, Yonga…☆16Jan 3, 2022Updated 4 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆15Nov 9, 2014Updated 11 years ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Oct 1, 2022Updated 3 years ago
- STONNE: A Simulation Tool for Neural Networks Engines☆147Jun 16, 2025Updated 8 months ago
- An analytical framework that models hardware dataflow of tensor applications on spatial architectures using the relation-centric notation…☆87Apr 28, 2024Updated last year
- Simulator for BitFusion☆101Aug 6, 2020Updated 5 years ago
- A DSL for Systolic Arrays☆83Dec 14, 2018Updated 7 years ago
- Full State Quantum Circuit Simulation Beyond Memory Limit☆15Aug 5, 2024Updated last year
- A simulation framework for modeling efficiency of Graph Neural Network Dataflows☆23Feb 14, 2025Updated last year
- Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation (ICCAD 2024)☆37Jun 17, 2025Updated 8 months ago
- Release of stream-specialization software/hardware stack.☆120May 5, 2023Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Sep 27, 2024Updated last year
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Jul 26, 2024Updated last year
- An FPGA Accelerator for Transformer Inference☆93Apr 29, 2022Updated 3 years ago
- Fast Floating Point Operators for High Level Synthesis☆24Feb 23, 2023Updated 3 years ago
- Heterogenous ML accelerator☆20May 5, 2025Updated 9 months ago
- ☆16Apr 10, 2023Updated 2 years ago
- An analytical cost model evaluating DNN mappings (dataflows and tiling).☆247Apr 15, 2024Updated last year
- Open-source of MSD framework☆16Sep 12, 2023Updated 2 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆97Oct 2, 2021Updated 4 years ago
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆23Jul 29, 2022Updated 3 years ago
- ☆11Mar 14, 2023Updated 2 years ago
- ☆21Oct 26, 2022Updated 3 years ago
- An HLS based winograd systolic CNN accelerator☆54Jul 18, 2021Updated 4 years ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆239Dec 8, 2022Updated 3 years ago