Alternatives and similar repositories for chipgptft:

Users that are interested in chipgptft are comparing it to the libraries listed below

• aichipdesign / chipgptv
  Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation (ICCAD 2024)
  ☆16Updated 6 months ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆39Updated 4 months ago
• UCLA-VAST / AutoDSE
  ACM TODAES Best Paper Award, 2022
  ☆24Updated last year
• hkust-zhiyao / RTLLM
  An open-source benchmark for generating design RTL with natural language
  ☆77Updated 2 months ago
• actlab-genesys / GeneSys
  An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
  ☆38Updated 3 weeks ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆85Updated 2 months ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆84Updated 4 months ago
• JBlocklove / LLMs-for-EDA-Tutorial
  ☆46Updated 3 months ago
• mit-emze / cimloop
  ☆50Updated last week
• UCLA-VAST / GNN-DSE
  DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"
  ☆40Updated last year
• zhaijw18 / mcpat-calib-public
  A RISC-V BOOM Microarchitecture Power Modeling Framework
  ☆23Updated last year
• pku-dasys / easymac
  ☆16Updated 2 years ago
• hngenc / stellar
  ☆22Updated 2 months ago
• hkust-zhiyao / PANDA
  PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions
  ☆14Updated last year
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆58Updated 2 weeks ago
• arc-research-lab / SSR
  SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)
  ☆28Updated 6 months ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆67Updated 3 years ago
• yhqiu16 / TRAM
  Template-based Reconfigurable Architecture Modeling Framework
  ☆13Updated 2 years ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆77Updated 6 months ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆47Updated this week
• maestro-project / gamma
  ☆39Updated 7 months ago
• tancheng / VectorCGRA
  CGRA framework with vectorization support.
  ☆21Updated this week
• isakedo / DNNsim
  ☆32Updated 4 years ago
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆41Updated 10 months ago
• pnnl / soda-opt
  ☆39Updated 7 months ago
• UT-LCA / ML4Accel-Dataset
  Dataset for ML-guided Accelerator Design
  ☆34Updated 2 months ago
• sjtu-zhao-lab / hierarchical-gnn-for-hls
  DATE'24 paper: "Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs"
  ☆14Updated last month
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆42Updated 2 years ago
• Accelergy-Project / processing-in-memory-design
  ☆25Updated 9 months ago
• sharc-lab / LightningSim
  A fast, accurate trace-based simulator for High-Level Synthesis.
  ☆40Updated 8 months ago