aichipdesign / chipgptftLinks
Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)
☆48Updated 9 months ago
Alternatives and similar repositories for chipgptft
Users that are interested in chipgptft are comparing it to the libraries listed below
Sorting:
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- An open-source benchmark for generating design RTL with natural language☆130Updated 10 months ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆63Updated 6 months ago
- ☆53Updated 3 months ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆68Updated 5 months ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆54Updated 3 months ago
- An Open-Source Tool for CGRA Accelerators☆72Updated last week
- ☆16Updated 3 years ago
- Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation (ICCAD 2024)☆27Updated 3 months ago
- A toolchain for rapid design space exploration of chiplet architectures☆59Updated last month
- ☆31Updated 10 months ago
- ☆58Updated 5 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆84Updated last year
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆33Updated this week
- Dataset for ML-guided Accelerator Design☆38Updated 10 months ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated 11 months ago
- ☆14Updated last year
- OriGen: Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection(ICCAD 2024)☆23Updated 10 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆63Updated last month
- Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".☆52Updated 3 months ago
- ☆13Updated 2 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆61Updated 11 months ago
- ACM TODAES Best Paper Award, 2022☆28Updated last year
- DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"☆40Updated last year
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆58Updated 2 months ago
- This is a python repo for flattening Verilog☆19Updated 4 months ago
- ☆49Updated 2 months ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆40Updated last week
- ☆37Updated last year
- An integrated CGRA design framework☆90Updated 6 months ago