Alternatives and similar repositories for haddoc2

Users that are interested in haddoc2 are comparing it to the libraries listed below

• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆105Updated 7 years ago
• Xilinx / SDSoC_Examples
  ☆84Updated 4 years ago
• Xilinx / PYNQ-DL
  Xilinx Deep Learning IP
  ☆92Updated 4 years ago
• Avnet / Ultra96-PYNQ
  Board files to build Ultra 96 PYNQ image
  ☆155Updated 6 months ago
• hirayaku / DAC2018-TGIIF
  The 1st place winner's source codes for DAC 2018 System Design Contest, FPGA Track
  ☆89Updated 6 years ago
• Xilinx / SDSoC-Tutorials
  SDSoC™ (Software-Defined System-On-Chip) Environment Tutorials
  ☆154Updated 5 years ago
• fpgasystems / ZipML-PYNQ
  Linear model training using stochastic gradient descent (SGD) on PYNQ with full to low precision.
  ☆55Updated 7 years ago
• Xilinx / RFNoC-HLS-NeuralNet
  ☆108Updated 5 years ago
• brianhill11 / FPGA-CNN
  This repo is for ECE44x (Fall2015-Spring2016)
  ☆20Updated 7 years ago
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆73Updated last year
• awai54st / LUTNet
  ☆58Updated 5 years ago
• Xilinx / logicnets
  Train and deploy LUT-based neural networks on FPGAs
  ☆97Updated last year
• CSL-KU / firesim-nvdla
  FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud
  ☆162Updated 3 years ago
• romulus0914 / CNN_VGG19_verilog
  Convolution Neural Network of vgg19 model in verilog
  ☆49Updated 7 years ago
• Xilinx / LSTM-PYNQ
  ☆89Updated 5 years ago
• hillhao / PYNQ-project
  PYNQ, Neural network Language model, Overlay
  ☆109Updated 6 years ago
• mohaghasemzadeh / ReBNet
  Residual Binarized Neural Network
  ☆43Updated 7 years ago
• chenhaoc / cnnhwpe
  ☆66Updated 3 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆65Updated 6 years ago
• onioncc / iSmartDNN
  Light-weighted neural network inference for object detection on small-scale FPGA board
  ☆91Updated 6 years ago
• gewuek / vitis_ai_custom_platform_flow
  This project is trying to create a base vitis platform to run with DPU
  ☆47Updated 5 years ago
• StefanSredojevic / Deep-Neural-Network-Hardware-Accelerator
  SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…
  ☆110Updated 5 years ago
• cornell-zhang / facedetect-fpga
  ☆44Updated 5 years ago
• PeterOgden / overlay_tutorial
  Premade bitstreams and block designs to complemented the PYNQ overlay tutorial
  ☆40Updated 3 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• alan4186 / Hardware-CNN
  A convolutional neural network implemented in hardware (verilog)
  ☆159Updated 7 years ago
• drichmond / RISC-V-On-PYNQ
  RISC-V Integration for PYNQ
  ☆175Updated 6 years ago
• xiangze / CNN_FPGA
  verilog CNN generator for FPGA
  ☆34Updated 4 years ago
• FelixWinterstein / Vivado-KMeans
  Hand-written HDL code and C-based HLS designs for K-means clustering implementations on FPGAs
  ☆48Updated 7 years ago
• hsharma35 / dnnweaver2
  Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.
  ☆216Updated 6 years ago