gkrish19 / SIAM-Chiplet-based-Scalable-In-Memory-Acceleration-with-Mesh-for-Deep-Neural-NetworksView on GitHub
A comprehensive tool that allows for system-level performance estimation of chiplet-based In-Memory computing (IMC) architectures.
☆25Jun 27, 2024Updated 2 years ago
Alternatives and similar repositories for SIAM-Chiplet-based-Scalable-In-Memory-Acceleration-with-Mesh-for-Deep-Neural-Networks
Users that are interested in SIAM-Chiplet-based-Scalable-In-Memory-Acceleration-with-Mesh-for-Deep-Neural-Networks are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A toolchain for rapid design space exploration of chiplet architectures☆89Jul 25, 2025Updated last year
- ☆16May 1, 2026Updated 4 months ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆116Apr 28, 2025Updated last year
- Neural Network-Hardware Co-design for Scalable RRAM-based BNN Accelerators☆11Apr 9, 2019Updated 7 years ago
- gem5 repository to study chiplet-based systems☆91Apr 18, 2019Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- HISIM introduces a suite of analytical models at the system level to speed up performance prediction for AI models, covering logic-on-log…☆65Updated this week
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆16Sep 24, 2020Updated 5 years ago
- A Python reference implementation of rigid body dynamics algorithms☆18Jul 17, 2023Updated 3 years ago
- ☆37Jun 4, 2024Updated 2 years ago
- Architecture for RRAM multilevel programming☆18Sep 6, 2018Updated 7 years ago
- Scalable In-Memory Acceleration With Mesh: Device, Circuits, Architecture, and Algorithm☆15Oct 11, 2020Updated 5 years ago
- A list of our chiplet simulaters☆51Jun 22, 2025Updated last year
- H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference☆117Apr 26, 2025Updated last year
- Official code of paper "MICSim: A Modular Simulator for Mixed-signal Compute-in-Memory based AI Accelerator", ASP-DAC 2025☆39Oct 15, 2025Updated 10 months ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆16Jan 6, 2023Updated 3 years ago
- MNSIM_Python_v1.0. The former circuits-level version link: https://github.com/Zhu-Zhenhua/MNSIM_V1.1☆35Jan 5, 2024Updated 2 years ago
- ☆28Aug 31, 2023Updated 3 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.☆33Feb 11, 2024Updated 2 years ago
- TBNv2: Convolutional Neural Network With Ternary Inputs and Binary Weights☆18Mar 4, 2020Updated 6 years ago
- ☆29Feb 18, 2020Updated 6 years ago
- Converting Boolean expressions to CMOS Circuits☆11Oct 6, 2020Updated 5 years ago
- Repository to host and maintain SCALE-Sim code☆515Jun 28, 2026Updated 2 months ago
- ☆32Feb 20, 2024Updated 2 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- We will be open sourcing a tool called FARSI (Facebook AR system investigator), a design space exploration framework. FARSI enables an ag…☆33Oct 30, 2022Updated 3 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆56Updated this week
- Computational Memory Neural Network Compiler☆11Aug 11, 2021Updated 5 years ago
- O'Reilly Course, In-Memory Computing Essentials☆10Oct 16, 2020Updated 5 years ago
- ☆24Apr 20, 2024Updated 2 years ago
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆265Oct 6, 2022Updated 3 years ago
- SimplePIM is the first high-level programming framework for real-world processing-in-memory (PIM) architectures. Described in the PACT 20…☆37Oct 23, 2023Updated 2 years ago
- Reproduction of WAGE in PyTorch.☆45Nov 18, 2018Updated 7 years ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆86Mar 12, 2025Updated last year
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- ☆68Jun 3, 2025Updated last year
- ☆53Dec 10, 2024Updated last year
- ☆35Jun 7, 2021Updated 5 years ago
- ☆16Jun 28, 2021Updated 5 years ago
- Repository for the tools and non-commercial data used for the "Accelerator wall" paper.☆51Jan 26, 2019Updated 7 years ago
- unsigned Radix-2 SRT division,基2除法☆17May 12, 2015Updated 11 years ago
- ☆66Oct 14, 2025Updated 10 months ago