gkrish19 / SIAM-Chiplet-based-Scalable-In-Memory-Acceleration-with-Mesh-for-Deep-Neural-NetworksView on GitHub
A comprehensive tool that allows for system-level performance estimation of chiplet-based In-Memory computing (IMC) architectures.
☆25Jun 27, 2024Updated 2 years ago
Alternatives and similar repositories for SIAM-Chiplet-based-Scalable-In-Memory-Acceleration-with-Mesh-for-Deep-Neural-Networks
Users that are interested in SIAM-Chiplet-based-Scalable-In-Memory-Acceleration-with-Mesh-for-Deep-Neural-Networks are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A toolchain for rapid design space exploration of chiplet architectures☆86Jul 25, 2025Updated 11 months ago
- Neural Network-Hardware Co-design for Scalable RRAM-based BNN Accelerators☆11Apr 9, 2019Updated 7 years ago
- gem5 repository to study chiplet-based systems☆90Apr 18, 2019Updated 7 years ago
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆14Sep 24, 2020Updated 5 years ago
- ☆29Aug 4, 2025Updated 11 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A Python reference implementation of rigid body dynamics algorithms☆18Jul 17, 2023Updated 2 years ago
- A Benchmark Suite for Real-Time Robotics☆14May 3, 2023Updated 3 years ago
- HISIM introduces a suite of analytical models at the system level to speed up performance prediction for AI models, covering logic-on-log…☆66Mar 29, 2026Updated 3 months ago
- A list of our chiplet simulaters☆50Jun 22, 2025Updated last year
- ☆37Jun 4, 2024Updated 2 years ago
- Architecture for RRAM multilevel programming☆18Sep 6, 2018Updated 7 years ago
- ☆65Jun 3, 2025Updated last year
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆41Mar 1, 2019Updated 7 years ago
- BSQ: Exploring Bit-Level Sparsity for Mixed-Precision Neural Network Quantization (ICLR 2021)☆41Jan 12, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- MNSIM_Python_v1.0. The former circuits-level version link: https://github.com/Zhu-Zhenhua/MNSIM_V1.1☆35Jan 5, 2024Updated 2 years ago
- ☆28Aug 31, 2023Updated 2 years ago
- ☆51Dec 10, 2024Updated last year
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.☆29Feb 11, 2024Updated 2 years ago
- TBNv2: Convolutional Neural Network With Ternary Inputs and Binary Weights☆18Mar 4, 2020Updated 6 years ago
- ☆28Feb 18, 2020Updated 6 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network☆47Aug 6, 2020Updated 5 years ago
- HW accelerator mapping optimization framework for in-memory computing☆29Jun 3, 2025Updated last year
- ☆31Feb 20, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Converting Boolean expressions to CMOS Circuits☆11Oct 6, 2020Updated 5 years ago
- We will be open sourcing a tool called FARSI (Facebook AR system investigator), a design space exploration framework. FARSI enables an ag…☆33Oct 30, 2022Updated 3 years ago
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆263Oct 6, 2022Updated 3 years ago
- ☆24Apr 20, 2024Updated 2 years ago
- O'Reilly Course, In-Memory Computing Essentials☆10Oct 16, 2020Updated 5 years ago
- SimplePIM is the first high-level programming framework for real-world processing-in-memory (PIM) architectures. Described in the PACT 20…☆36Oct 23, 2023Updated 2 years ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆83Mar 12, 2025Updated last year
- Reproduction of WAGE in PyTorch.☆45Nov 18, 2018Updated 7 years ago
- Computational Memory Neural Network Compiler☆11Aug 11, 2021Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆34Jun 7, 2021Updated 5 years ago
- Repository to host and maintain SCALE-Sim code☆483Jun 27, 2026Updated last week
- Automatic generation of FPGA-based learning accelerators for the neural network family☆69Dec 26, 2019Updated 6 years ago
- Repository for the tools and non-commercial data used for the "Accelerator wall" paper.☆52Jan 26, 2019Updated 7 years ago
- EE 272B - VLSI Design Project☆15Jun 24, 2021Updated 5 years ago
- unsigned Radix-2 SRT division,基2除法☆17May 12, 2015Updated 11 years ago
- The wafer-native AI accelerator simulation platform and inference engine.☆56Jan 1, 2026Updated 6 months ago