gkrish19 / SIAM-Chiplet-based-Scalable-In-Memory-Acceleration-with-Mesh-for-Deep-Neural-NetworksLinks
A comprehensive tool that allows for system-level performance estimation of chiplet-based In-Memory computing (IMC) architectures.
☆23Updated last year
Alternatives and similar repositories for SIAM-Chiplet-based-Scalable-In-Memory-Acceleration-with-Mesh-for-Deep-Neural-Networks
Users that are interested in SIAM-Chiplet-based-Scalable-In-Memory-Acceleration-with-Mesh-for-Deep-Neural-Networks are comparing it to the libraries listed below
Sorting:
- A list of our chiplet simulaters☆38Updated 2 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- An integrated CGRA design framework☆90Updated 6 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆63Updated last month
- The open-sourced version of BOOM-Explorer☆43Updated 2 years ago
- RTL implementation of Flex-DPE.☆110Updated 5 years ago
- ☆42Updated 3 months ago
- An Open-Source Tool for CGRA Accelerators☆72Updated last week
- A reading list for SRAM-based Compute-In-Memory (CIM) research.☆82Updated 3 months ago
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆41Updated 4 years ago
- ☆17Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated 11 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 3 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆16Updated last year
- RTL generator for SpGEMM☆11Updated 4 years ago
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆29Updated 2 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆84Updated last year
- eyeriss-chisel3☆41Updated 3 years ago
- An FPGA Accelerator for Transformer Inference☆88Updated 3 years ago
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 3 years ago
- ☆17Updated 4 months ago
- A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0☆33Updated last month
- ☆116Updated 5 years ago
- ☆43Updated last month
- A co-design architecture on sparse attention☆51Updated 4 years ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆155Updated this week
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆63Updated 9 months ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆73Updated 6 months ago
- MICRO22 artifact evaluation for Sparseloop☆44Updated 3 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆58Updated 2 months ago