chipsalliance / silicon-notebooksLinks
☆173Updated 2 years ago
Alternatives and similar repositories for silicon-notebooks
Users that are interested in silicon-notebooks are comparing it to the libraries listed below
Sorting:
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆198Updated last month
- Fully Open Source FASOC generators built on top of open-source EDA tools☆302Updated last month
- Fabric generator and CAD tools.☆214Updated this week
- ☆85Updated 3 years ago
- ASIC implementation flow infrastructure, successor to OpenLane☆216Updated this week
- ☆122Updated 2 years ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆321Updated 2 weeks ago
- https://caravel-user-project.readthedocs.io☆224Updated 9 months ago
- Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs☆74Updated last month
- ☆183Updated 4 years ago
- ☆366Updated 2 years ago
- Qflow full end-to-end digital synthesis flow for ASIC designs☆223Updated last year
- Course material for a basic hands-on analog circuit design course with IC emphasis☆170Updated last week
- ☆44Updated 9 months ago
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆377Updated last week
- SystemVerilog synthesis tool☆220Updated 9 months ago
- Hardware Description Library☆88Updated 8 months ago
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆369Updated 9 months ago
- This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is …☆160Updated last year
- OpenROAD users should look at this repository first for instructions on getting started☆101Updated 4 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆175Updated this week
- Standard Cell Library based Memory Compiler using FF/Latch cells☆162Updated last month
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆118Updated 4 years ago
- A complete open-source design-for-testing (DFT) Solution☆173Updated 3 months ago
- Curriculum for a university course to teach chip design using open source EDA tools☆125Updated 2 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆67Updated 3 years ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆307Updated 2 months ago
- Index of the fully open source process design kits (PDKs) maintained by Google.☆108Updated 3 years ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆275Updated last week
- FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already ins…☆104Updated last year