StefanSchippers / xschem
A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
☆362Updated this week
Alternatives and similar repositories for xschem:
Users that are interested in xschem are comparing it to the libraries listed below
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆308Updated 3 weeks ago
- 130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design☆463Updated this week
- Magic VLSI Layout Tool☆510Updated this week
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆267Updated this week
- Fully Open Source FASOC generators built on top of open-source EDA tools☆259Updated this week
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆312Updated last week
- FOSS Flow For FPGA☆369Updated last month
- IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively s…☆418Updated last week
- The Xyce™ Parallel Electronic Simulator☆34Updated 2 weeks ago
- Qflow full end-to-end digital synthesis flow for ASIC designs☆198Updated 3 months ago
- This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is …☆147Updated 8 months ago
- UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …☆385Updated this week
- Learning to do things with the Skywater 130nm process☆76Updated 4 years ago
- An abstraction library for interfacing EDA tools☆663Updated last week
- OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/☆380Updated this week
- https://caravel-user-project.readthedocs.io☆191Updated 2 weeks ago
- PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).☆379Updated last year
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆381Updated 2 months ago
- EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)☆146Updated 2 months ago
- ☆309Updated last year
- ☆109Updated last year
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆280Updated this week
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆172Updated last month
- OpenSTA engine☆433Updated this week
- A huge VHDL library for FPGA development☆372Updated this week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆209Updated 3 months ago
- An open-source static random access memory (SRAM) compiler.☆873Updated 3 months ago
- OpenROAD users should look at this repository first for instructions on getting started☆102Updated 3 years ago
- SystemVerilog to Verilog conversion☆591Updated this week
- OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...☆235Updated last week