StefanSchippers / xschem
A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
☆366Updated this week
Alternatives and similar repositories for xschem:
Users that are interested in xschem are comparing it to the libraries listed below
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆311Updated last month
- Magic VLSI Layout Tool☆515Updated 2 weeks ago
- Fully Open Source FASOC generators built on top of open-source EDA tools☆264Updated 3 weeks ago
- 130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design☆479Updated this week
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆275Updated 2 weeks ago
- Qflow full end-to-end digital synthesis flow for ASIC designs☆201Updated 4 months ago
- FOSS Flow For FPGA☆375Updated 2 months ago
- The Xyce™ Parallel Electronic Simulator☆36Updated last week
- PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).☆385Updated last year
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆318Updated 2 weeks ago
- https://caravel-user-project.readthedocs.io☆193Updated 2 weeks ago
- ☆314Updated last year
- IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively s…☆436Updated this week
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆280Updated last week
- OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/☆385Updated this week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆382Updated last week
- ☆109Updated last year
- Netgen complete LVS tool for comparing SPICE or verilog netlists☆113Updated this week
- Example designs showing different ways to use F4PGA toolchains.☆272Updated 11 months ago
- UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …☆388Updated 3 weeks ago
- Learning to do things with the Skywater 130nm process☆76Updated 4 years ago
- SystemVerilog to Verilog conversion☆600Updated 2 weeks ago
- ☆136Updated 3 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆211Updated this week
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆174Updated 2 months ago
- OpenSTA engine☆441Updated 2 weeks ago
- ☆286Updated this week
- This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is …☆147Updated 9 months ago
- Multi-platform nightly builds of open source digital design and verification tools☆978Updated this week
- Fabric generator and CAD tools☆162Updated 2 weeks ago