efabless / caravel_user_projectLinks
https://caravel-user-project.readthedocs.io
☆216Updated 6 months ago
Alternatives and similar repositories for caravel_user_project
Users that are interested in caravel_user_project are comparing it to the libraries listed below
Sorting:
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆347Updated 6 months ago
- ☆343Updated 2 years ago
- This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is …☆156Updated last year
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆354Updated last week
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆312Updated 6 months ago
- Qflow full end-to-end digital synthesis flow for ASIC designs☆217Updated 10 months ago
- Fully Open Source FASOC generators built on top of open-source EDA tools☆288Updated 2 months ago
- Fabric generator and CAD tools.☆196Updated this week
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆187Updated last month
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆291Updated 3 months ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆156Updated 2 months ago
- VeeR EL2 Core☆297Updated 2 weeks ago
- ☆115Updated 2 years ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆163Updated 2 years ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆137Updated 3 years ago
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆188Updated 3 months ago
- CORE-V Family of RISC-V Cores☆293Updated 7 months ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆324Updated 9 months ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆231Updated last week
- OpenROAD users should look at this repository first for instructions on getting started☆101Updated 4 years ago
- RISC-V Verification Interface☆102Updated 3 months ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆116Updated 4 years ago
- FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already ins…☆99Updated last year
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆65Updated 2 years ago
- SystemVerilog synthesis tool☆209Updated 6 months ago
- ☆171Updated 4 years ago
- ☆83Updated 2 years ago
- An overview of TL-Verilog resources and projects☆82Updated 5 months ago
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆293Updated this week
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆263Updated 2 weeks ago