efabless / caravel_user_project
https://caravel-user-project.readthedocs.io
☆196Updated last month
Alternatives and similar repositories for caravel_user_project:
Users that are interested in caravel_user_project are comparing it to the libraries listed below
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆319Updated last month
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆314Updated 2 months ago
- Fully Open Source FASOC generators built on top of open-source EDA tools☆269Updated this week
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆276Updated last month
- ☆110Updated last year
- Qflow full end-to-end digital synthesis flow for ASIC designs☆205Updated 5 months ago
- ☆316Updated last year
- Standard Cell Library based Memory Compiler using FF/Latch cells☆144Updated 9 months ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆272Updated last week
- VeeR EL2 Core☆272Updated this week
- Fabric generator and CAD tools☆164Updated last week
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆175Updated 2 weeks ago
- This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is …☆149Updated 10 months ago
- CORE-V Family of RISC-V Cores☆249Updated last month
- FuseSoC-based SoC for VeeR EH1 and EL2☆310Updated 3 months ago
- 130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design☆508Updated this week
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆246Updated last month
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆157Updated last year
- Common SystemVerilog components☆599Updated 3 weeks ago
- OpenROAD users should look at this repository first for instructions on getting started☆101Updated 4 years ago
- ☆139Updated 3 years ago
- Test suite designed to check compliance with the SystemVerilog standard.☆311Updated this week
- PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).☆389Updated last year
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆243Updated this week
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆137Updated 2 years ago
- ☆79Updated 2 years ago
- EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)☆152Updated last week
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆265Updated 4 years ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆134Updated 6 months ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆216Updated last week