Alternatives and similar repositories for caravel_user_project

Users that are interested in caravel_user_project are comparing it to the libraries listed below

• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆376Updated 11 months ago
• idea-fasoc / OpenFASOC
  Fully Open Source FASOC generators built on top of open-source EDA tools
  ☆308Updated 3 months ago
• chipfoundry / openlane2
  The next generation of OpenLane, rewritten from scratch with a modular architecture
  ☆331Updated 2 months ago
• efabless / OpenLane
  This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is …
  ☆161Updated last year
• mattvenn / awesome-opensource-asic-resources
  ☆375Updated 2 years ago
• RTimothyEdwards / open_pdks
  PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…
  ☆389Updated last month
• RTimothyEdwards / qflow
  Qflow full end-to-end digital synthesis flow for ASIC designs
  ☆223Updated last year
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆164Updated 2 months ago
• google / sky90fd-pdk
  ☆122Updated 2 years ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆195Updated last month
• librelane / librelane
  ASIC implementation flow infrastructure, successor to OpenLane
  ☆268Updated last week
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆316Updated last month
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆215Updated this week
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆320Updated 11 months ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆309Updated 3 months ago
• kunalg123 / vsdflow
  VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…
  ☆164Updated 2 years ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆334Updated last year
• The-OpenROAD-Project / OPENROAD_USERS_READ_ME_FIRST
  OpenROAD users should look at this repository first for instructions on getting started
  ☆101Updated 4 years ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆226Updated 10 months ago
• AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
  ☆74Updated 3 years ago
• sscs-ose / sscs-ose-code-a-chip.github.io
  IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)
  ☆202Updated 3 weeks ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆201Updated this week
• google / open-source-pdks
  Index of the fully open source process design kits (PDKs) maintained by Google.
  ☆109Updated 3 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆170Updated 6 years ago
• ncsu-eda / FreePDK3
  ☆189Updated 4 years ago
• chipsalliance / silicon-notebooks
  ☆173Updated 2 years ago
• TL-X-org / TL-V_Projects
  An overview of TL-Verilog resources and projects
  ☆82Updated last month
• akilm / Physical-Design
  Physical Design Flow from RTL to GDS using Opensource tools.
  ☆118Updated 5 years ago
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆301Updated this week
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆178Updated 5 months ago