efabless / caravel_user_projectLinks
https://caravel-user-project.readthedocs.io
☆206Updated 4 months ago
Alternatives and similar repositories for caravel_user_project
Users that are interested in caravel_user_project are comparing it to the libraries listed below
Sorting:
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆338Updated 4 months ago
- This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is …☆152Updated last year
- ☆112Updated 2 years ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆301Updated 4 months ago
- Fully Open Source FASOC generators built on top of open-source EDA tools☆283Updated 2 weeks ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆151Updated last week
- ☆333Updated 2 years ago
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆337Updated 2 weeks ago
- OpenROAD users should look at this repository first for instructions on getting started☆101Updated 4 years ago
- Qflow full end-to-end digital synthesis flow for ASIC designs☆216Updated 8 months ago
- Fabric generator and CAD tools.☆190Updated this week
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆283Updated last month
- VeeR EL2 Core☆288Updated 2 weeks ago
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆186Updated last month
- ☆79Updated 2 years ago
- ☆150Updated 3 years ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆257Updated 4 months ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆161Updated 2 years ago
- Index of the fully open source process design kits (PDKs) maintained by Google.☆99Updated 2 years ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆181Updated 3 weeks ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆64Updated 2 years ago
- A complete open-source design-for-testing (DFT) Solution☆161Updated last month
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆139Updated 2 years ago
- CORE-V Family of RISC-V Cores☆278Updated 5 months ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆137Updated 3 years ago
- SystemVerilog synthesis tool☆201Updated 4 months ago
- OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/☆455Updated this week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆221Updated 2 weeks ago
- RISC-V microcontroller IP core developed in Verilog☆174Updated 3 months ago
- Basic RISC-V Test SoC☆137Updated 6 years ago