klasnordmark / openlane-examplesLinks
Examples from the Openlane repository, adapted as Fusesoc cores
☆12Updated 4 years ago
Alternatives and similar repositories for openlane-examples
Users that are interested in openlane-examples are comparing it to the libraries listed below
Sorting:
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- ☆37Updated 2 years ago
- An automatic clock gating utility☆49Updated 2 months ago
- ☆31Updated last year
- Open source RTL simulation acceleration on commodity hardware☆28Updated 2 years ago
- ☆32Updated 5 months ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 4 years ago
- KLayout technology files for ASAP7 FinFET educational process☆20Updated 2 years ago
- A configurable SRAM generator☆51Updated last week
- A padring generator for ASICs☆25Updated 2 years ago
- Characterizer☆24Updated last month
- ☆20Updated 3 years ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 7 months ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated 11 months ago
- ☆33Updated 5 years ago
- FPGA250 aboard the eFabless Caravel☆30Updated 4 years ago
- USB virtual model in C++ for Verilog☆31Updated 8 months ago
- Design of 4KB Static RAM 1.8V (access time <2.5ns) using OpenRAM and Sky130 node☆14Updated 4 years ago
- An open source PDK using TIGFET 10nm devices.☆48Updated 2 years ago
- Instrumenting adders to measure speed☆13Updated 3 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆49Updated 7 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last year
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆22Updated 6 months ago
- Gate-level visualization generator for SKY130-based chip designs.☆19Updated 3 years ago
- ☆44Updated 5 years ago
- SRAM☆22Updated 4 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆33Updated 2 weeks ago
- SystemVerilog Linter based on pyslang☆31Updated last month
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated 11 months ago
- ☆19Updated 11 years ago