klasnordmark / openlane-examplesLinks
Examples from the Openlane repository, adapted as Fusesoc cores
☆12Updated 4 years ago
Alternatives and similar repositories for openlane-examples
Users that are interested in openlane-examples are comparing it to the libraries listed below
Sorting:
- ☆38Updated 3 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆34Updated last year
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 5 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- ☆20Updated 4 years ago
- ☆33Updated 11 months ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- An open source PDK using TIGFET 10nm devices.☆54Updated 2 years ago
- AMC: Asynchronous Memory Compiler☆51Updated 5 years ago
- Open source process design kit for 28nm open process☆68Updated last year
- ☆20Updated last year
- ☆44Updated 5 years ago
- ☆31Updated 2 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆43Updated 2 years ago
- An automatic clock gating utility☆51Updated 8 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- A configurable SRAM generator☆56Updated 3 months ago
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆48Updated last year
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- KLayout technology files for ASAP7 FinFET educational process☆23Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 5 months ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆28Updated 10 months ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- Bitstream relocation and manipulation tool.☆50Updated 3 years ago
- Open Source PHY v2☆31Updated last year
- Prefix tree adder space exploration library☆56Updated last year
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆24Updated 4 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆40Updated last week
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆23Updated 5 years ago