klasnordmark / openlane-examplesLinks
Examples from the Openlane repository, adapted as Fusesoc cores
☆12Updated 4 years ago
Alternatives and similar repositories for openlane-examples
Users that are interested in openlane-examples are comparing it to the libraries listed below
Sorting:
- ☆38Updated 3 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated last year
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 5 years ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- ☆20Updated 3 years ago
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- ☆31Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- ☆33Updated 9 months ago
- An automatic clock gating utility☆50Updated 6 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆43Updated 2 years ago
- ☆44Updated 5 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated 2 years ago
- AMC: Asynchronous Memory Compiler☆51Updated 5 years ago
- Open source process design kit for 28nm open process☆66Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 4 months ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 10 years ago
- Library of open source Process Design Kits (PDKs)☆56Updated 2 weeks ago
- An open source PDK using TIGFET 10nm devices.☆51Updated 2 years ago
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- A configurable SRAM generator☆56Updated 2 months ago
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆30Updated 12 years ago
- Design of 4KB Static RAM 1.8V (access time <2.5ns) using OpenRAM and Sky130 node☆14Updated 4 years ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆25Updated 3 months ago
- Open Source PHY v2☆31Updated last year
- ☆85Updated 2 weeks ago
- ☆18Updated last year
- KLayout technology files for ASAP7 FinFET educational process☆21Updated 2 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆48Updated 11 months ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆89Updated last year