efabless / proton

Related projects ⓘ

Alternatives and complementary repositories for proton

• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆31Updated 3 months ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated last year
• trusster / trusster
  Hardware Verification library for C++, SystemC and SystemVerilog
  ☆27Updated 11 years ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆46Updated 9 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆28Updated 3 months ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆33Updated 8 years ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆16Updated 2 years ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆41Updated 8 months ago
• yash-k99 / vsdsram
  Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM
  ☆19Updated 4 years ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆31Updated 2 weeks ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆39Updated last year
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 8 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆34Updated 7 months ago
• woset-workshop / woset-workshop.github.io
  Workshop on Open-Source EDA Technology (WOSET)
  ☆45Updated this week
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆21Updated 4 years ago
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆15Updated 2 weeks ago
• ucb-bar / OpenSoCFabric
  OpenSoC Fabric - A Network-On-Chip Generator
  ☆17Updated 7 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆22Updated last year
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆46Updated 4 years ago
• ieee-ceda-datc / datc-rdf-calibrations
  ☆16Updated last week
• thesourcerer8 / StdCellLib
  LibreSilicon's Standard Cell Library Generator
  ☆17Updated 6 months ago
• dh73 / A_Formal_Tale_Chapter_I_AMBA
  AXI Formal Verification IP
  ☆19Updated 3 years ago
• povik / yosys-slang
  slang-based frontend for Yosys
  ☆41Updated this week
• jbush001 / PASC
  Parallel Array of Simple Cores. Multicore processor.
  ☆92Updated 5 years ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆25Updated 4 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆39Updated 4 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆53Updated last year
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated last year