efabless / protonLinks
☆33Updated 5 years ago
Alternatives and similar repositories for proton
Users that are interested in proton are comparing it to the libraries listed below
Sorting:
- A collection of big designs to run post-synthesis simulations with yosys☆51Updated 10 years ago
- ☆38Updated 3 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆44Updated 2 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Builds, flow and designs for the alpha release☆54Updated 6 years ago
- An automatic clock gating utility☆51Updated 8 months ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- Python interface to FPGA interchange format☆41Updated 3 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- An open source PDK using TIGFET 10nm devices.☆54Updated 3 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- Facilitates building open source tools for working with hardware description languages (HDLs)☆66Updated 6 years ago
- OpenSoC Fabric - A Network-On-Chip Generator☆18Updated 8 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- KLayout technology files for ASAP7 FinFET educational process☆23Updated 2 years ago
- AMC: Asynchronous Memory Compiler☆51Updated 5 years ago
- ☆20Updated last year
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 2 months ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆18Updated last year
- ☆31Updated 2 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆38Updated 2 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆87Updated 4 years ago
- ☆57Updated 2 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆47Updated last week
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 9 years ago
- ☆33Updated 11 months ago
- Yet Another RISC-V Implementation☆99Updated last year