Alternatives and similar repositories for aws-fpga-firesim

Users that are interested in aws-fpga-firesim are comparing it to the libraries listed below

• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆57Updated 5 years ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆64Updated 6 years ago
• steveicarus / ivtest
  Regression test suite for Icarus Verilog. (OBSOLETE)
  ☆115Updated 2 years ago
• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆82Updated 2 months ago
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆41Updated 6 years ago
• x-epic / EpicSim
  EpicSim Project
  ☆71Updated 4 years ago
• SymbiFlow / vtr-verilog-to-routing
  SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆38Updated last year
• cornell-brg / lizard
  Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
  ☆88Updated 6 years ago
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆95Updated 3 years ago
• schoeberl / lipsi
  Lipsi: Probably the Smallest Processor in the World
  ☆86Updated last year
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆81Updated 5 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• malkadi / FGPU
  FGPU is a soft GPU architecture general purpose computing
  ☆60Updated 4 years ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆66Updated 5 years ago
• fpgasystems / Centaur
  Centaur, a framework for hybrid CPU-FPGA databases
  ☆27Updated 8 years ago
• eliaskousk / parallella-riscv
  RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
  ☆102Updated 6 years ago
• google / bottlerocket
  ☆109Updated 6 years ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆34Updated 9 years ago
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆54Updated 5 years ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆71Updated 5 years ago
• aliyun / alibabacloud-fpga
  ☆20Updated 5 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated 5 months ago
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆123Updated 3 months ago
• PulseRain / Rattlesnake
  PulseRain Rattlesnake - RISCV RV32IMC Soft CPU
  ☆34Updated 5 years ago
• corundum / verilog-pcie
  Verilog PCI express components
  ☆23Updated 2 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆147Updated 3 months ago
• torc-isi / torc
  Torc: Tools for Open Reconfigurable Computing
  ☆39Updated 8 years ago
• illustris / FreeRTOS-RISCV
  A port of FreeRTOS for the RISC-V ISA
  ☆77Updated 6 years ago
• fpgadeveloper / ethernet-fmc-zynq-gem
  Example design for the Ethernet FMC using the hard GEMs of the Zynq
  ☆57Updated 3 months ago
• furkanturan / lowrisc-zed
  LowRISC port to Zedboard
  ☆13Updated 8 years ago