firesim / aws-fpga-firesim
AWS Shell for FireSim
☆12Updated 2 months ago
Alternatives and similar repositories for aws-fpga-firesim:
Users that are interested in aws-fpga-firesim are comparing it to the libraries listed below
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- ☆63Updated 6 years ago
- ☆43Updated 3 weeks ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆25Updated 4 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- Extensible FPGA control platform☆55Updated last year
- SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research☆37Updated 4 months ago
- PCI Express controller model☆47Updated 2 years ago
- OmniXtend cache coherence protocol☆78Updated 4 years ago
- ☆31Updated last year
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆99Updated 6 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆98Updated last year
- RISC-V Nexus Trace TG documentation and reference code☆48Updated 2 weeks ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆82Updated 3 years ago
- ☆21Updated 7 years ago
- Yet Another RISC-V Implementation☆86Updated 3 months ago
- The OpenRISC 1000 architectural simulator☆72Updated 4 months ago
- SoCRocket - Core Repository☆34Updated 7 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆62Updated 4 years ago
- LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G☆33Updated last year
- Original RISC-V 1.0 implementation. Not supported.☆41Updated 6 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆79Updated 5 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆35Updated 2 years ago
- Centaur, a framework for hybrid CPU-FPGA databases☆27Updated 7 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆84Updated 5 years ago
- Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.☆18Updated 10 months ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆43Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆79Updated 5 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆79Updated 3 months ago