OpenPOWERFoundation / openpowerLinks
OpenPOWER Foundation General Information & Repository Listing
☆21Updated 3 years ago
Alternatives and similar repositories for openpower
Users that are interested in openpower are comparing it to the libraries listed below
Sorting:
- The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …☆47Updated 3 weeks ago
- IRSIM switch-level simulator for digital circuits☆34Updated last month
- ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆34Updated this week
- The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers☆44Updated 2 years ago
- 🌄 RISC-V Ecosystem Landscape: a living document that developers, investors, vendors, researchers and others can use as a resource on the…☆15Updated this week
- Documentation developer guide☆103Updated 2 weeks ago
- ☆29Updated 3 years ago
- RISC-V Configuration Validator☆79Updated 2 months ago
- Main Repo for the OpenHW Group Software Task Group☆17Updated 2 months ago
- Unofficial Yosys WebAssembly packages☆71Updated last week
- ☆30Updated 3 weeks ago
- ☆24Updated 10 months ago
- The ISA specification for the ZiCondOps extension.☆19Updated last year
- ☆36Updated 3 weeks ago
- Kuchen Computer☆23Updated 11 months ago
- RTL blocks compatible with the Rocket Chip Generator☆16Updated 2 months ago
- RISC-V SMBIOS Type 44 Spec☆12Updated last year
- OpenSPARC-based SoC☆67Updated 10 years ago
- This repository contains sample code integrating Renode with Verilator☆19Updated last week
- cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.☆106Updated this week
- An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …☆46Updated 9 months ago
- The Boot and Runtime Services (BRS) specification provides the software requirements for system vendors and Operating System Vendors (OSV…☆49Updated 3 weeks ago
- Custom 64-bit pipelined RISC processor☆18Updated 10 months ago
- This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory prot…☆68Updated 2 weeks ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆146Updated 7 months ago
- 😎 A curated list of awesome RISC-V implementations☆136Updated 2 years ago
- YoWASP toolchain for Visual Studio Code☆19Updated 4 months ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- Assemble 128-bit RISC-V☆45Updated last year
- A full micro-controller system utilizing the CHERIoT Ibex core, part of the Sunburst project funded by UKRI☆41Updated this week