OpenPOWERFoundation / openpowerLinks
OpenPOWER Foundation General Information & Repository Listing
β22Updated 3 years ago
Alternatives and similar repositories for openpower
Users that are interested in openpower are comparing it to the libraries listed below
Sorting:
- Documentation developer guideβ112Updated 2 weeks ago
- π RISC-V Ecosystem Landscape: a living document that developers, investors, vendors, researchers and others can use as a resource on theβ¦β17Updated this week
- β30Updated last week
- A full micro-controller system utilizing the CHERIoT Ibex core, part of the Sunburst project funded by UKRIβ45Updated this week
- 4 stage, in-order, secure RISC-V core based on the CV32E40Pβ147Updated 9 months ago
- OpenSPARC-based SoCβ68Updated 11 years ago
- β62Updated 4 years ago
- The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, β¦β49Updated 2 months ago
- The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputersβ45Updated 2 years ago
- The ISA specification for the ZiCondOps extension.β19Updated last year
- β30Updated last month
- β42Updated 9 months ago
- FPGA Assembly (FASM) Parser and Generatorβ95Updated 3 years ago
- FPGA tool performance profilingβ102Updated last year
- The Boot and Runtime Services (BRS) specification provides the software requirements for system vendors and Operating System Vendors (OSVβ¦β52Updated 2 weeks ago
- RISC-V Configuration Validatorβ80Updated 4 months ago
- RISC-V Processor Trace Specificationβ191Updated last week
- This repository provides a Linux kernel bootable on RISC-V boards from SiFiveβ169Updated 5 years ago
- β149Updated last year
- Documentation for OpenPOWER Firmwareβ72Updated last year
- β89Updated 3 years ago
- The multi-core cluster of a PULP system.β105Updated this week
- Main Repo for the OpenHW Group Software Task Groupβ17Updated 5 months ago
- π A curated list of awesome RISC-V implementationsβ137Updated 2 years ago
- β17Updated last year
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.β85Updated 2 months ago
- Workshop on Computer Architecture Research with RISC-V (CARRV)β41Updated 9 months ago
- βοΈ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.β34Updated this week
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MITβ32Updated last week
- CV32E40X Design-Verification environmentβ12Updated last year