OpenPOWERFoundation / openpower
OpenPOWER Foundation General Information & Repository Listing
☆21Updated 3 years ago
Alternatives and similar repositories for openpower
Users that are interested in openpower are comparing it to the libraries listed below
Sorting:
- The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …☆46Updated last year
- The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers☆44Updated 2 years ago
- IRSIM switch-level simulator for digital circuits☆34Updated last month
- The ISA specification for the ZiCondOps extension.☆19Updated last year
- An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …☆48Updated 8 months ago
- 🌄 RISC-V Ecosystem Landscape: a living document that developers, investors, vendors, researchers and others can use as a resource on the…☆15Updated this week
- Main Repo for the OpenHW Group Software Task Group☆17Updated 2 months ago
- RISC-V Configuration Validator☆79Updated last month
- RTL blocks compatible with the Rocket Chip Generator☆16Updated last month
- ☆34Updated 2 weeks ago
- ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆34Updated this week
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆27Updated last year
- Graphics SIG organizational information☆39Updated last year
- An example OMI Device FPGA with 2 DDR4 memory ports☆16Updated 2 years ago
- A multi-threaded microprocessor interleaving as minimum two threads, which is pin-to-pin compatible with pulpino riscy cores☆26Updated 8 months ago
- ☆32Updated 6 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆145Updated 6 months ago
- ☆25Updated 2 months ago
- ☆12Updated last year
- ☆30Updated last week
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆32Updated last week
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆36Updated 3 years ago
- ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 archite…☆78Updated 2 years ago
- ☆61Updated 4 years ago
- Documentation for F4PGA☆23Updated last year
- Synthesisable SIMT-style RISC-V GPGPU☆33Updated last month
- nextpnr portable FPGA place and route tool☆20Updated 8 months ago
- Unofficial Yosys WebAssembly packages☆70Updated last week
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated last year
- RISC-V Core Local Interrupt Controller (CLINT)☆26Updated last year