Alternatives and similar repositories for cynq

Users that are interested in cynq are comparing it to the libraries listed below

• MakarenaLabs / Xilinx-FPGA-HLS-PYNQ-ALVEO-Flow
  Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.
  ☆30Updated 5 years ago
• sharc-lab / HLSFactory
  HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond
  ☆39Updated 3 weeks ago
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆87Updated 2 months ago
• brigio345 / DaCH
  DaCH: dataflow cache for high-level synthesis.
  ☆18Updated 2 years ago
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆51Updated 2 years ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆53Updated 10 months ago
• cathalmccabe / PYNQ_tutorials
  ☆94Updated last year
• Xilinx / SLASH
  A research shell for Alveo V80
  ☆17Updated 3 weeks ago
• Xilinx / logicnets
  Train and deploy LUT-based neural networks on FPGAs
  ☆97Updated last year
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆73Updated last year
• IMPETUS-UdeS / rule4ml
  Resource Utilization and Latency Estimation for ML on FPGA.
  ☆15Updated 3 weeks ago
• arc-research-lab / AIM
  AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…
  ☆24Updated 2 months ago
• rapidstream-org / rapidstream-tapa
  RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.
  ☆173Updated this week
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 5 years ago
• cjg91 / trans-fat
  An FPGA Accelerator for Transformer Inference
  ☆88Updated 3 years ago
• Sibylau / HLS_designs
  Systolic array implementations for Cholesky, LU, and QR decomposition
  ☆45Updated 9 months ago
• hlslibs / ac_ml
  Algorithmic C Machine Learning Library
  ☆26Updated 7 months ago
• enyac-group / MaxEVA
  MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)
  ☆21Updated last year
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆77Updated 2 years ago
• UCLA-VAST / FlexCNN
  ☆72Updated 2 years ago
• esl-epfl / OpenEdgeCGRA
  An Open-Hardware CGRA for accelerated computation on the edge.
  ☆30Updated 11 months ago
• rockyco / pulseDetector
  LLM-Aided FPGA Design for Signal Processing Applications
  ☆27Updated 2 months ago
• gnodipac886 / ViT-FPGA-TPU
  FPGA based Vision Transformer accelerator (Harvard CS205)
  ☆123Updated 6 months ago
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆67Updated 5 years ago
• ehw-fit / evoapproxlib
  Library of approximate arithmetic circuits
  ☆55Updated 2 years ago
• sharc-lab / FPGA_ECE8893
  ☆36Updated 4 months ago
• jefflieu / HLS-Tiny-Tutorials
  This is forked from Xilinx HLS-Tiny-Tutorial. I'm learning HLS and adding Verilator testbench to verify the generated RTL
  ☆27Updated 3 years ago
• AlexMontgomerie / fpgaconvnet-model
  Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.
  ☆30Updated 9 months ago
• awai54st / LUTNet
  ☆58Updated 5 years ago
• ahirsharan / 32-Bit-Floating-Point-Adder
  Verilog Implementation of 32-bit Floating Point Adder
  ☆40Updated 5 years ago