makslevental / openhls
PyTorch model to RTL flow for low latency inference
☆125Updated 11 months ago
Alternatives and similar repositories for openhls:
Users that are interested in openhls are comparing it to the libraries listed below
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆77Updated 7 months ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆212Updated 2 years ago
- A scalable High-Level Synthesis framework on MLIR☆250Updated 9 months ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆121Updated this week
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆135Updated 2 weeks ago
- A DSL for Systolic Arrays☆79Updated 6 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆55Updated 3 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆48Updated this week
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆142Updated 2 years ago
- ☆41Updated last week
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆165Updated this week
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆48Updated 3 weeks ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆130Updated 2 months ago
- The codes and artifacts associated with our MICRO'22 paper titled: "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware …☆123Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆86Updated 5 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆68Updated 5 years ago
- ☆47Updated 3 weeks ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆72Updated last month
- ☆23Updated 7 months ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆63Updated last week
- ☆87Updated last year
- A matrix extension proposal for AI applications under RISC-V architecture☆128Updated last month
- RTL implementation of Flex-DPE.☆98Updated 5 years ago
- STONNE: A Simulation Tool for Neural Networks Engines☆125Updated 9 months ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆100Updated last year
- Release of stream-specialization software/hardware stack.☆120Updated last year
- ☆84Updated 9 months ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆20Updated 6 months ago
- Fork of upstream onnxruntime focused on supporting risc-v accelerators☆83Updated last year
- Public release☆49Updated 5 years ago