makslevental / openhlsLinks
PyTorch model to RTL flow for low latency inference
☆129Updated last year
Alternatives and similar repositories for openhls
Users that are interested in openhls are comparing it to the libraries listed below
Sorting:
- A DSL for Systolic Arrays☆82Updated 6 years ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆224Updated 2 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators.☆175Updated 2 months ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆158Updated this week
- ☆60Updated 7 months ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆140Updated 4 months ago
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆163Updated last week
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆160Updated 2 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆87Updated last year
- A scalable High-Level Synthesis framework on MLIR☆282Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- ☆60Updated this week
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆75Updated 3 weeks ago
- ☆63Updated 6 months ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆126Updated 2 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆60Updated 3 years ago
- Train and deploy LUT-based neural networks on FPGAs☆100Updated last year
- ☆37Updated 7 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆61Updated 3 months ago
- ☆72Updated 2 years ago
- ☆50Updated 4 months ago
- An Open-Source Tool for CGRA Accelerators☆74Updated last month
- NeuraLUT-Assemble☆43Updated 2 months ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆167Updated last year
- A hardware synthesis framework with multi-level paradigm☆41Updated 9 months ago
- RTL implementation of Flex-DPE.☆113Updated 5 years ago
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆49Updated 3 months ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆96Updated this week
- An Open-Hardware CGRA for accelerated computation on the edge.☆35Updated last year