makslevental / openhlsLinks
PyTorch model to RTL flow for low latency inference
☆131Updated last year
Alternatives and similar repositories for openhls
Users that are interested in openhls are comparing it to the libraries listed below
Sorting:
- A DSL for Systolic Arrays☆81Updated 6 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆137Updated 3 months ago
- AutoSA: Polyhedral-Based Systolic Array Compiler☆223Updated 2 years ago
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators.☆174Updated last month
- A scalable High-Level Synthesis framework on MLIR☆275Updated last year
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆157Updated 3 weeks ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆74Updated 3 weeks ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆155Updated this week
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆160Updated 2 years ago
- ☆49Updated 2 months ago
- An Open-Source Tool for CGRA Accelerators☆73Updated last week
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated 11 months ago
- ☆58Updated 5 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆58Updated 2 months ago
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆47Updated last month
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆84Updated last year
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆86Updated 3 months ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆35Updated last year
- ☆63Updated 4 months ago
- ☆61Updated this week
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆61Updated 11 months ago
- Train and deploy LUT-based neural networks on FPGAs☆98Updated last year
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆124Updated 2 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆63Updated last month
- NeuraLUT-Assemble☆41Updated last month
- An integrated CGRA design framework☆90Updated 6 months ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆48Updated 6 months ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆59Updated 3 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆200Updated 5 years ago
- ☆87Updated last year