USB 2.0 FS Device controller IP core written in SystemVerilog
☆41Dec 2, 2018Updated 7 years ago
Alternatives and similar repositories for usb20dev
Users that are interested in usb20dev are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- USB 2.0 Device IP Core☆75Oct 1, 2017Updated 8 years ago
- USB 1.1 Host and Function IP core☆27Jul 17, 2014Updated 12 years ago
- Test of the USB3 IP Core from Daisho on a Xilinx device☆110Oct 3, 2019Updated 6 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Dec 9, 2020Updated 5 years ago
- USB Full-Speed/Hi-Speed Device Controller core for FPGA☆34Nov 23, 2020Updated 5 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Verilog-Based-NoC-Simulator☆12May 4, 2016Updated 10 years ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆15Jan 4, 2019Updated 7 years ago
- USB -> AXI Debug Bridge☆46Jun 5, 2021Updated 5 years ago
- Collaborative project to create an advanced GPU, with additional features to flesh-out the peripherals for a home-made, DIY computer.☆18Feb 26, 2023Updated 3 years ago
- Python Verilog-AMS Parser☆12Oct 13, 2015Updated 10 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆16Jan 22, 2025Updated last year
- ☆13Nov 5, 2017Updated 8 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆22Nov 21, 2017Updated 8 years ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- YosysHQ SVA AXI Properties☆54Feb 7, 2023Updated 3 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆49Jan 14, 2021Updated 5 years ago
- PCI bridge☆20Jul 17, 2014Updated 12 years ago
- A full-speed device-side USB peripheral core written in Verilog.☆242Oct 30, 2022Updated 3 years ago
- Contains source code for sin/cos table verification using UVM☆23Mar 9, 2021Updated 5 years ago
- Basic USB-CDC device core (Verilog)☆93May 15, 2021Updated 5 years ago
- SystemVerilog examples and projects☆21Jun 10, 2025Updated last year
- A collection of SPI related cores☆22Nov 12, 2024Updated last year
- Theia: ray graphic processing unit☆20Jul 17, 2014Updated 12 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 5 years ago
- Simple demo showing how to use the ping pong FIFO☆17May 2, 2016Updated 10 years ago
- Full Speed USB DFU interface for FPGA and ASIC designs☆21Mar 10, 2024Updated 2 years ago
- USB3 PIPE interface for Xilinx 7-Series☆269Apr 3, 2026Updated 4 months ago
- Delta-sigma ADC,PDM audio FPGA Implementation☆76Jun 16, 2022Updated 4 years ago
- USB2.0 Device Controller IP Core☆18Aug 18, 2023Updated 2 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Dec 26, 2022Updated 3 years ago
- MMC (and derivative standards) host controller☆26Sep 14, 2020Updated 5 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆33Jun 22, 2024Updated 2 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Repository gathering basic modules for CDC purpose☆63Dec 31, 2019Updated 6 years ago
- Generic AXI master stub☆20Jul 17, 2014Updated 12 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Updated this week
- RISCV CPU implementation in SystemVerilog☆32Jul 24, 2026Updated 2 weeks ago
- Examples and reference for System Verilog Assertions☆92Mar 18, 2017Updated 9 years ago
- An Open Source Link Protocol and Controller☆29Aug 1, 2021Updated 5 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆42Oct 16, 2017Updated 8 years ago