USB 2.0 FS Device controller IP core written in SystemVerilog
☆39Dec 2, 2018Updated 7 years ago
Alternatives and similar repositories for usb20dev
Users that are interested in usb20dev are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- USB 2.0 Device IP Core☆75Oct 1, 2017Updated 8 years ago
- USB 1.1 Host and Function IP core☆25Jul 17, 2014Updated 11 years ago
- Test of the USB3 IP Core from Daisho on a Xilinx device☆103Oct 3, 2019Updated 6 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Dec 9, 2020Updated 5 years ago
- USB Full-Speed/Hi-Speed Device Controller core for FPGA☆34Nov 23, 2020Updated 5 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆14Jan 4, 2019Updated 7 years ago
- Verilog-Based-NoC-Simulator☆10May 4, 2016Updated 9 years ago
- Collaborative project to create an advanced GPU, with additional features to flesh-out the peripherals for a home-made, DIY computer.☆18Feb 26, 2023Updated 3 years ago
- USB -> AXI Debug Bridge☆43Jun 5, 2021Updated 4 years ago
- Python Verilog-AMS Parser☆12Oct 13, 2015Updated 10 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- A collection of SPI related cores☆21Nov 12, 2024Updated last year
- ☆14Nov 5, 2017Updated 8 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆22Nov 21, 2017Updated 8 years ago
- Wordpress hosting with auto-scaling on Cloudways • AdFully Managed hosting built for WordPress-powered businesses that need reliable, auto-scalable hosting. Cloudways SafeUpdates now available.
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- YosysHQ SVA AXI Properties☆49Feb 7, 2023Updated 3 years ago
- UVM components for DSP tasks (MODulation/DEModulation)☆15Mar 2, 2022Updated 4 years ago
- A full-speed device-side USB peripheral core written in Verilog.☆237Oct 30, 2022Updated 3 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆46Jan 14, 2021Updated 5 years ago
- Contains source code for sin/cos table verification using UVM☆21Mar 9, 2021Updated 5 years ago
- SystemVerilog examples and projects☆20Jun 10, 2025Updated 10 months ago
- Basic USB-CDC device core (Verilog)☆89May 15, 2021Updated 4 years ago
- an sata controller using smallest resource.☆17Feb 5, 2014Updated 12 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- Theia: ray graphic processing unit☆20Jul 17, 2014Updated 11 years ago
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 4 years ago
- An Example implementation of Open Source Graphics Accelerator, (A fixed point, fixed function pipeline GPU)☆76Jun 7, 2012Updated 13 years ago
- Delta-sigma ADC,PDM audio FPGA Implementation☆74Jun 16, 2022Updated 3 years ago
- USB3 PIPE interface for Xilinx 7-Series☆252Apr 3, 2026Updated last week
- Repository gathering basic modules for CDC purpose☆60Dec 31, 2019Updated 6 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆30Dec 26, 2022Updated 3 years ago
- Full Speed USB DFU interface for FPGA and ASIC designs☆20Mar 10, 2024Updated 2 years ago
- MMC (and derivative standards) host controller☆25Sep 14, 2020Updated 5 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆34Jun 22, 2024Updated last year
- PCI bridge☆20Jul 17, 2014Updated 11 years ago
- Generic AXI master stub☆19Jul 17, 2014Updated 11 years ago
- Utilities for Avalon Memory Map☆11Jul 11, 2024Updated last year
- RISCV CPU implementation in SystemVerilog☆32Mar 17, 2026Updated 3 weeks ago
- An Open Source Link Protocol and Controller☆28Aug 1, 2021Updated 4 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆42Oct 16, 2017Updated 8 years ago