esynr3z / usb20devLinks
USB 2.0 FS Device controller IP core written in SystemVerilog
☆39Updated 7 years ago
Alternatives and similar repositories for usb20dev
Users that are interested in usb20dev are comparing it to the libraries listed below
Sorting:
- USB Full Speed PHY☆48Updated 5 years ago
- TCP/IP controlled VPI JTAG Interface.☆69Updated last year
- Basic USB 1.1 Host Controller for small FPGAs☆97Updated 5 years ago
- Ethernet MAC 10/100 Mbps☆31Updated 4 years ago
- Wishbone interconnect utilities☆44Updated last month
- Wishbone controlled I2C controllers☆57Updated last year
- Minimal DVI / HDMI Framebuffer☆84Updated 5 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆33Updated 5 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆86Updated last year
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆79Updated 3 years ago
- Basic USB-CDC device core (Verilog)☆86Updated 4 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆97Updated 3 years ago
- USB -> AXI Debug Bridge☆42Updated 4 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆72Updated 7 years ago
- USB 1.1 Host and Function IP core☆24Updated 11 years ago
- MMC (and derivative standards) host controller☆25Updated 5 years ago
- Extensible FPGA control platform☆61Updated 2 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 5 years ago
- Universal Advanced JTAG Debug Interface☆17Updated last year
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆46Updated 5 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆42Updated 2 years ago
- Spen's Official OpenOCD Mirror☆51Updated 11 months ago
- SPI-Flash XIP Interface (Verilog)☆48Updated 4 years ago
- ☆41Updated 4 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆97Updated 5 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆83Updated 5 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated 2 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 10 years ago
- JTAG Test Access Port (TAP)☆37Updated 11 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago