waviousllc / wav-slink-hwLinks
An Open Source Link Protocol and Controller
☆27Updated 4 years ago
Alternatives and similar repositories for wav-slink-hw
Users that are interested in wav-slink-hw are comparing it to the libraries listed below
Sorting:
- An Open Source Link Protocol and Controller☆25Updated 4 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆35Updated this week
- An open source PDK using TIGFET 10nm devices.☆49Updated 2 years ago
- UVM components for DSP tasks (MODulation/DEModulation)☆14Updated 3 years ago
- ☆17Updated 9 months ago
- Open FPGA Modules☆24Updated 10 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- ☆59Updated 3 years ago
- high level VHDL floating point library for synthesis in fpga☆18Updated 5 months ago
- ☆18Updated 4 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆28Updated 9 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last month
- ☆33Updated 2 years ago
- Source-Opened RISCV for Crypto☆16Updated 3 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆19Updated 3 years ago
- ☆10Updated last year
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆48Updated 4 years ago
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆23Updated 5 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆106Updated 4 years ago
- Virtual development board for HDL design☆42Updated 2 years ago
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 8 years ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 8 months ago
- Common SystemVerilog RTL modules for RgGen☆13Updated 2 months ago
- tools regarding on analog modeling, validation, and generation☆22Updated 2 years ago
- CMake based hardware build system☆30Updated 2 weeks ago
- Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…☆18Updated 7 years ago
- LibreSilicon's Standard Cell Library Generator☆20Updated last year