waviousllc / wav-slink-hw

Related projects ⓘ

Alternatives and complementary repositories for wav-slink-hw

• IObundle / iob-lib
  Verilog Modules and Python Scripts for Creating IP Core Build Directories
  ☆29Updated last year
• SLink-Protocol / S-Link
  An Open Source Link Protocol and Controller
  ☆23Updated 3 years ago
• pulp-platform / apb
  APB Logic
  ☆12Updated 9 months ago
• pulp-platform / axi_llc
  ☆21Updated 2 months ago
• semify-eda / fstdumper
  Verilog VPI module to dump FST (Fast Signal Trace) databases
  ☆16Updated last year
• SeanZarzycki / openSPARC-FPU
  ASIC Design of the openSPARC Floating Point Unit
  ☆13Updated 7 years ago
• dpretet / svlogger
  SystemVerilog Logger
  ☆16Updated 2 years ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆23Updated last week
• vlotnik / uvm_modem
  UVM components for DSP tasks (MODulation/DEModulation)
  ☆14Updated 2 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated last year
• YosysHQ / padring
  A padring generator for ASICs
  ☆22Updated last year
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆28Updated last week
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆39Updated last year
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆28Updated 4 months ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆26Updated 9 years ago
• FPGA-Research-Manchester / byteman
  Bitstream relocation and manipulation tool.
  ☆40Updated last year
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆30Updated 3 years ago
• CESNET / ofm
  Open FPGA Modules
  ☆23Updated last month
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆17Updated last year
• dbhi / vboard
  Virtual development board for HDL design
  ☆39Updated last year
• shalan / Chameleon_SoC
  AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...
  ☆12Updated 3 years ago
• mohamed / fsm2sv
  SystemVerilog FSM generator
  ☆26Updated 6 months ago
• pulp-platform / adv_dbg_if
  Advanced Debug Interface
  ☆12Updated last year
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆30Updated last year
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆28Updated last month
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆35Updated last week
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆28Updated 3 weeks ago
• waviousllc / wav-lpddr-sw
  Wavious DDR (WDDR) Physical interface (PHY) Software
  ☆19Updated 2 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆24Updated last year
• hVHDL / hVHDL_floating_point
  high level VHDL floating point library for synthesis in fpga
  ☆15Updated 4 months ago