waviousllc / wav-slink-hwLinks
An Open Source Link Protocol and Controller
☆27Updated 4 years ago
Alternatives and similar repositories for wav-slink-hw
Users that are interested in wav-slink-hw are comparing it to the libraries listed below
Sorting:
- An Open Source Link Protocol and Controller☆27Updated 4 years ago
- An open source PDK using TIGFET 10nm devices.☆51Updated 2 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆37Updated last week
- Open FPGA Modules☆24Updated last year
- ☆32Updated 2 years ago
- LibreSilicon's Standard Cell Library Generator☆20Updated last week
- ☆17Updated 11 months ago
- LMAC Core1 - Ethernet 1G/100M/10M☆18Updated 2 years ago
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆14Updated 6 months ago
- tools regarding on analog modeling, validation, and generation☆22Updated 2 years ago
- UVM components for DSP tasks (MODulation/DEModulation)☆14Updated 3 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 10 months ago
- ☆60Updated 4 years ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆28Updated 8 months ago
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆18Updated 6 months ago
- SGMII☆13Updated 11 years ago
- ☆18Updated 5 years ago
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆23Updated 5 years ago
- Source-Opened RISCV for Crypto☆18Updated 3 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 5 years ago
- Virtual development board for HDL design☆42Updated 2 years ago
- LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G☆40Updated 2 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 9 years ago
- FPGA250 aboard the eFabless Caravel☆31Updated 4 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- Bitstream relocation and manipulation tool.☆47Updated 2 years ago
- An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…☆11Updated 5 years ago