Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
☆22Nov 21, 2017Updated 8 years ago
Alternatives and similar repositories for QuickSPI
Users that are interested in QuickSPI are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A Xilinx IP Core and App for line scanner image capture and store☆11Sep 5, 2017Updated 8 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆43Jan 18, 2024Updated 2 years ago
- A 32 point radix-2 FFT module written in Verilog☆25Jun 28, 2020Updated 5 years ago
- A ZipCPU demonstration port for the icoboard☆19Oct 21, 2021Updated 4 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆25Jul 6, 2018Updated 7 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Various projects of SPI loader module for xilinx fpga☆33Jul 20, 2020Updated 5 years ago
- USB -> AXI Debug Bridge☆44Jun 5, 2021Updated 4 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆99Oct 31, 2022Updated 3 years ago
- This is a SPI Master Module Written in Verilog☆14Aug 9, 2018Updated 7 years ago
- MEEP FPGA Shell project, currently supporting Alveos u280 and u55c☆16Mar 14, 2024Updated 2 years ago
- ESnet general-purpose FPGA design library.☆14Updated this week
- AXI3 Bus Functional Models (Initiator & Target)☆29Dec 26, 2022Updated 3 years ago
- SPI-Flash XIP Interface (Verilog)☆49Oct 24, 2021Updated 4 years ago
- Matlab implementation of polar codes for a BEC☆11Dec 1, 2017Updated 8 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- USB 2.0 FS Device controller IP core written in SystemVerilog☆41Dec 2, 2018Updated 7 years ago
- ☆20Jun 18, 2022Updated 3 years ago
- USB 1.1 Host and Function IP core☆26Jul 17, 2014Updated 11 years ago
- 适用于FPGA——利用串口通信接收幅度频率信息数据帧，控制DA输出相应正弦信号☆10Jul 10, 2019Updated 6 years ago
- 基于Verilog实现的串口发送程序，带奇偶校验位。☆12Aug 23, 2019Updated 6 years ago
- A PicoRV32 SoC for the TinyFPGA BX with peripherals designed for building games☆24Nov 15, 2018Updated 7 years ago
- A complete 65C02 computer with VGA output on a Lattice Ultra Plus FPGA☆29Jun 12, 2019Updated 6 years ago
- Verilog RS232 Enhanced Synch-UART & RS232 Debugger HDL core with PC host RS232 real-time Hex-editor / viewer host utility.☆12Jan 15, 2022Updated 4 years ago
- APB Logic☆25Feb 24, 2026Updated 2 months ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- RISC-V Nox core☆73Jul 22, 2025Updated 9 months ago
- ☆13May 21, 2019Updated 6 years ago
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆21Sep 5, 2021Updated 4 years ago
- Wishbone to ARM AMBA 4 AXI☆16May 25, 2019Updated 6 years ago
- A 4x4x4 Tic-Tac-Toe game suitable for porting to embedded hardware platforms☆11Sep 6, 2017Updated 8 years ago
- [READ ONLY] Subtree split of the siyuan-packages-monorepo (see https://github.com/Zuoqiu-Yingyi/siyuan-packages-monorepo)☆12Jan 23, 2024Updated 2 years ago
- ☆16Jan 12, 2021Updated 5 years ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- Basic USB-CDC device core (Verilog)☆89May 15, 2021Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- LDPC编码解码matlab代码和Verilog代码及资料☆51Aug 27, 2018Updated 7 years ago
- Generic AXI master stub☆19Jul 17, 2014Updated 11 years ago
- A simple 6502 system built on a Lattice Ultra Plus 5k FPGA☆15Mar 11, 2019Updated 7 years ago
- Uses the D8M camera module, then processes the image to detect red objects, and then overlay an x,y crosshair on the largest red object. …☆15Jan 19, 2018Updated 8 years ago
- The TV80 (Verilog) synthesizable soft core of Zilog Z80 (forked from http://opencores.org/project,tv80)☆10Jan 9, 2016Updated 10 years ago
- Project and presentation for SpaceX Application☆14Jul 21, 2017Updated 8 years ago
- MATLAB implementation of the DVB-S2 as in ETSI EN 302 307-1☆15Aug 26, 2021Updated 4 years ago