MJoergen / AvalonView external linksLinks
Utilities for Avalon Memory Map
☆11Jul 11, 2024Updated last year
Alternatives and similar repositories for Avalon
Users that are interested in Avalon are comparing it to the libraries listed below
Sorting:
- Portable HyperRAM controller☆65Dec 8, 2024Updated last year
- Implementation of FM (frequency modulation) radio transmitter in FPGA Altera Cyclone III.☆14May 16, 2016Updated 9 years ago
- SDR-Transceiver☆10Dec 30, 2019Updated 6 years ago
- SHA-1,SHA-256,SHA-512 Secure Hash Generator written in VHDL(RTL) for FPGA(Xilinx and Altera).☆12Oct 14, 2017Updated 8 years ago
- Drive a Wishbone master bus with an SPI bus.☆10Apr 24, 2025Updated 9 months ago
- FPGA-based I2C to RS-232 serial converter / bus monitor☆13Jan 29, 2016Updated 10 years ago
- ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)☆13Aug 29, 2018Updated 7 years ago
- ☆18Oct 5, 2020Updated 5 years ago
- A lightweight Ethernet MAC Controller IP for FPGA prototyping☆14Oct 19, 2020Updated 5 years ago
- Wishbone to AXI bridge (VHDL)☆44Aug 29, 2019Updated 6 years ago
- Groundhog - Serial ATA Host Bus Adapter☆24Jun 10, 2018Updated 7 years ago
- This repository contains IPs, Vitis kernels and software APIs that can be leveraged by Vitis users to build scale-out solutions on multip…☆23Apr 27, 2023Updated 2 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆16May 26, 2021Updated 4 years ago
- ☆21Jul 28, 2021Updated 4 years ago
- This is the repository for a verilog implementation of a lzrw1 compression core☆19Dec 8, 2017Updated 8 years ago
- "Very low cost, tiny (USB thumb size) FPGA board. 1st board with Efinix Trion FPGA and comes with Efinity IDE Solder or unsoldered versio…☆25Nov 11, 2019Updated 6 years ago
- An open-source VHDL library for FPGA design.☆32Jun 2, 2022Updated 3 years ago
- ☆20Jun 18, 2022Updated 3 years ago
- VHDL String Formatting Library☆27Apr 27, 2024Updated last year
- vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.☆26Jan 7, 2016Updated 10 years ago
- Centaur, a framework for hybrid CPU-FPGA databases☆28May 2, 2017Updated 8 years ago
- Triple Modular Redundancy☆28Sep 4, 2019Updated 6 years ago
- Various projects of SPI loader module for xilinx fpga☆33Jul 20, 2020Updated 5 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆30Dec 26, 2022Updated 3 years ago
- USB Full-Speed/Hi-Speed Device Controller core for FPGA☆33Nov 23, 2020Updated 5 years ago
- An infrastructure for inline acceleration of network applications☆30Oct 25, 2021Updated 4 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆82Oct 6, 2022Updated 3 years ago
- JESD204B core for Migen/MiSoC☆35May 5, 2021Updated 4 years ago
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆12Jul 14, 2024Updated last year
- A wishbone controlled scope for FPGA's☆87Jan 12, 2024Updated 2 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆42Jan 18, 2024Updated 2 years ago
- ☆13Jan 22, 2026Updated 3 weeks ago
- FPGA Low latency 10GBASE-R PCS☆12May 23, 2023Updated 2 years ago
- A project demonstrate how to config ad9361 to TX mode☆11Dec 9, 2018Updated 7 years ago
- ☆10Jun 26, 2025Updated 7 months ago
- mirror of https://git.elphel.com/Elphel/eddr3☆41Oct 16, 2017Updated 8 years ago
- Python script to transform a VCD file to wavedrom format☆84Aug 18, 2022Updated 3 years ago
- Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.☆39Oct 5, 2020Updated 5 years ago
- Sweet32 32bit MRISC CPU - VHDL and software toolchain sources (including documentation)☆38Oct 29, 2015Updated 10 years ago