dpretet / friscvLinks
RISCV CPU implementation in SystemVerilog
☆32Updated 2 months ago
Alternatives and similar repositories for friscv
Users that are interested in friscv are comparing it to the libraries listed below
Sorting:
- A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board☆31Updated 4 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆33Updated 2 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 3 years ago
- ☆14Updated 8 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆71Updated 3 weeks ago
- DUTH RISC-V Superscalar Microprocessor☆32Updated last year
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- ☆60Updated 4 years ago
- RISC-V Nox core☆70Updated 4 months ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Updated last month
- Synchronous FIFOs designed in Verilog/System Verilog.☆24Updated last month
- Ethernet MAC 10/100 Mbps☆29Updated 4 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆109Updated this week
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆51Updated last year
- ☆33Updated 3 years ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆31Updated 4 years ago
- Open FPGA Modules☆24Updated last year
- An Open Source Link Protocol and Controller☆27Updated 4 years ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Updated 2 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 5 months ago
- ☆40Updated last year
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆54Updated 2 years ago
- SPIR-V fragment shader GPU core based on RISC-V☆42Updated 4 years ago
- Another tiny RISC-V implementation☆62Updated 4 years ago
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆13Updated 8 months ago
- An implementation of RISC-V☆44Updated last week
- A Python package for generating HDL wrappers and top modules for HDL sources☆40Updated last week
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆26Updated last month