dpretet / friscvLinks
RISCV CPU implementation in SystemVerilog
☆32Updated 2 weeks ago
Alternatives and similar repositories for friscv
Users that are interested in friscv are comparing it to the libraries listed below
Sorting:
- A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board☆31Updated 4 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆33Updated 2 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆47Updated 3 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- ☆60Updated 4 years ago
- A configurable general purpose graphics processing unit for☆11Updated 6 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆50Updated 11 months ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 11 months ago
- An Open Source Link Protocol and Controller☆27Updated 4 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- ☆30Updated 3 weeks ago
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆19Updated 4 years ago
- ☆13Updated 2 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆66Updated last month
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆107Updated last month
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- This is a circular buffer controller used in FPGA.☆34Updated 9 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 5 years ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Updated 2 years ago
- Matrix multiplication accelerator on ZYNQ SoC.☆12Updated 5 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 3 months ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆25Updated 6 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆22Updated last year
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆52Updated last year
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆14Updated 6 months ago
- LIS Network-on-Chip Implementation☆31Updated 9 years ago
- Register-based and RAM-based FIFOs designed in Verilog/System Verilog.☆19Updated last year
- A Python package for generating HDL wrappers and top modules for HDL sources☆37Updated last week
- 256-bit vector processor based on the RISC-V vector (V) extension☆30Updated 4 years ago