Alternatives and similar repositories for eddr3

Users that are interested in eddr3 are comparing it to the libraries listed below

• freecores / wb_dma
  WISHBONE DMA/Bridge IP Core
  ☆18Updated 11 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆50Updated last year
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆32Updated 9 years ago
• CospanDesign / vivado-ip-cores
  IP Cores that can be used within Vivado
  ☆26Updated 4 years ago
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆16Updated 5 years ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆47Updated 10 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆21Updated 2 years ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆35Updated 7 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆84Updated 6 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆63Updated 4 years ago
• Elphel / x393_sata
  mirror of https://git.elphel.com/Elphel/x393_sata
  ☆33Updated 5 years ago
• marph91 / pico-png
  PNG encoder, implemented in VHDL
  ☆23Updated last year
• damdoy / fpga_image_processing
  IP operations in verilog (simulation and implementation on ice40)
  ☆61Updated 6 years ago
• bmartini / verilog-arbiter
  A look ahead, round-robing parametrized arbiter written in Verilog.
  ☆43Updated 5 years ago
• yigitbektasgursoy / SDRAM_Verilog
  Verilog HDL implementation of SDRAM controller and SDRAM model
  ☆31Updated last year
• fpgadeveloper / ethernet-fmc-axi-eth
  Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks
  ☆65Updated 5 months ago
• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 11 years ago
• ultraembedded / core_jpeg_decoder
  HW JPEG decoder wrapper with AXI-4 DMA
  ☆36Updated 5 years ago
• CospanDesign / nysa-verilog
  Verilog Repository for GIT
  ☆33Updated 4 years ago
• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆29Updated 2 years ago
• hellgate202 / csi2_rx
  MIPI CSI-2 RX
  ☆37Updated 4 years ago
• freecores / video_stream_scaler
  Video Stream Scaler
  ☆40Updated 11 years ago
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆47Updated last year
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆34Updated 8 months ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆60Updated 5 years ago
• manjushpv / Design-and-Verification-of-Nand-Flash-Memory-Controller
  - Designed a Nand Flash Controller, Flash Memory and Buffer (Design Target : Samsung K9F1G08R0A NAND Flash).
 - Implemented operations : …
  ☆21Updated 7 years ago
• AugustinJose1221 / FFTx32
  A 32 point radix-2 FFT module written in Verilog
  ☆23Updated 5 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆79Updated 3 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆60Updated 2 years ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆54Updated 5 years ago