Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
☆35Nov 3, 2025Updated 11 months ago
Alternatives and similar repositories for skid_buffer
Users that are interested in skid_buffer are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Synchronous FIFOs designed in Verilog/System Verilog.☆26Dec 21, 2025Updated 10 months ago
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆21Sep 5, 2021Updated 5 years ago
- ☆14Updated this week
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆14Apr 20, 2014Updated 12 years ago
- APB Logic☆29Sep 24, 2026Updated last month
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ☆39Oct 22, 2026Updated last week
- AXI3 Bus Functional Models (Initiator & Target)☆30Dec 26, 2022Updated 3 years ago
- A 32 point radix-2 FFT module written in Verilog☆25Jun 28, 2020Updated 6 years ago
- Generic FIFO implementation with optional FWFT☆65May 27, 2020Updated 6 years ago
- A light-weight hardware oriented synchronous stream cipher.☆12Mar 19, 2022Updated 4 years ago
- ☆10Mar 18, 2020Updated 6 years ago
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆19Dec 12, 2025Updated 10 months ago
- TMR utilities for the SpyDrNet project☆16Nov 7, 2023Updated 2 years ago
- SCARV: a side-channel hardened RISC-V platform☆28Jan 11, 2023Updated 3 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Universal Asynchronous Receiver/Transmitter (UART) with FIFOs Soft IP☆16Feb 18, 2025Updated last year
- Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…☆22Feb 4, 2025Updated last year
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆27Apr 11, 2022Updated 4 years ago
- Verilog PreProcessor.☆12Nov 9, 2015Updated 10 years ago
- Benchmarks for High-Level Synthesis☆11Mar 17, 2023Updated 3 years ago
- FPU Generator☆21Updated this week
- ☆10Feb 8, 2023Updated 3 years ago
- FPGA implementation of the Image stitching using FAST. For CPU implementation visit tharaka27-ImageStitcherFAST.☆12Aug 10, 2020Updated 6 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆35Jun 22, 2024Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Blackwire overview, status, roadmap and top-level documentation.☆17Aug 21, 2023Updated 3 years ago
- HeteroGen: transpiling C to heterogeneous HLS code with automated test generation and program repair (ASPLOS 2022)☆16Sep 25, 2024Updated 2 years ago
- HW Design Collateral for Caliptra RoT IP☆159Updated this week
- Simple hash table on Verilog (SystemVerilog)☆55Apr 3, 2016Updated 10 years ago
- Post-Quantum Cryptography IP Core (Crystals-Dilithium)☆69Updated this week
- Example design for the Ethernet FMC using an FPGA based hardware packet generator/checker to demonstrate maximum throughput☆12Oct 12, 2026Updated 2 weeks ago
- This Repo contains SystemC for testBench for AMBA® 3 AHB-Lite Protocol☆14Jul 11, 2018Updated 8 years ago
- DaCH: dataflow cache for high-level synthesis.☆20Jul 27, 2023Updated 3 years ago
- Core protocol to AXI bridge☆11Sep 30, 2019Updated 7 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A simple cycle-accurate DaDianNao simulator☆13Mar 27, 2019Updated 7 years ago
- ☆21Nov 18, 2022Updated 3 years ago
- The open-source release of "SpikeHard: Efficiency-Driven Neuromorphic Hardware for Heterogeneous Systems-on-Chip"☆11Oct 7, 2023Updated 3 years ago
- Python script for generating Xilinx .coe files for RAM initializing☆20Jan 3, 2019Updated 7 years ago
- File editor for the Xilinx AXI Traffic Generator IP☆17Feb 9, 2026Updated 8 months ago
- SPIR-V fragment shader GPU core based on RISC-V☆48May 26, 2021Updated 5 years ago
- DUTH RISC-V Superscalar Microprocessor☆35Oct 23, 2024Updated 2 years ago