baochuquan / RISCV-MMU
☆14Updated 7 years ago
Related projects ⓘ
Alternatives and complementary repositories for RISCV-MMU
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆29Updated 4 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 3 years ago
- SPI-Flash XIP Interface (Verilog)☆35Updated 3 years ago
- Ethernet MAC 10/100 Mbps☆24Updated 3 years ago
- ☆16Updated 5 years ago
- A 32-bit RISC-V SoC on FPGA that supports RT-Thread.☆22Updated last year
- DSP WishBone Compatible Cores☆13Updated 10 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆30Updated last year
- USB 1.1 Host and Function IP core☆19Updated 10 years ago
- ☆31Updated last year
- A small 32-bit implementation of the RISC-V architecture☆32Updated 4 years ago
- A RISC-V processor☆13Updated 5 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆20Updated 6 years ago
- 平头哥无剑100开源SoC平台(双核E902,安全启动,BootROM,IOPMP,Mailbox,RSA-2048,SHA-2, WS2812,Flash)☆14Updated last year
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆20Updated 4 years ago
- Generic AXI master stub☆19Updated 10 years ago
- This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…☆75Updated 4 years ago
- ☆20Updated 2 months ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- USB Full Speed PHY☆39Updated 4 years ago
- This script builds the UVM register model, based on pre-defined address map in markdown (mk) style☆12Updated 6 years ago
- It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.☆16Updated 4 years ago
- Educational 16-bit MIPS Processor☆16Updated 5 years ago
- DMA core compatible with AHB3-Lite☆10Updated 5 years ago
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆22Updated 6 years ago
- Helper scripts used to clone RISC-V related git repos inside China.☆14Updated 4 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆25Updated 9 years ago
- FIR,FFT based on Verilog☆13Updated 6 years ago
- turbo 8051☆28Updated 7 years ago
- Simple demo showing how to use the ping pong FIFO☆13Updated 8 years ago