USB Full-Speed/Hi-Speed Device Controller core for FPGA
☆34Nov 23, 2020Updated 5 years ago
Alternatives and similar repositories for USBCore
Users that are interested in USBCore are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- AXI-Stream USB 2.0 HS Device Bridge (Verilog)☆16Apr 17, 2025Updated last year
- FPGA-based I2C to RS-232 serial converter / bus monitor☆13Jan 29, 2016Updated 10 years ago
- FPGA USB 1.1 Low-Speed Implementation☆36Oct 3, 2018Updated 8 years ago
- Implementation of FM (frequency modulation) radio transmitter in FPGA Altera Cyclone III.☆14May 16, 2016Updated 10 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆104Jun 6, 2020Updated 6 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- A configurable USB 2.0 device core☆31Jun 12, 2020Updated 6 years ago
- High Speed USB 2.0 capture device based on miniSpartan6+☆60May 26, 2020Updated 6 years ago
- Universal Advanced JTAG Debug Interface☆17May 10, 2024Updated 2 years ago
- Xilinx Virtual Cable Daemon☆20Nov 20, 2019Updated 6 years ago
- Altera JTAG UART wrapper for Bluespec☆27Mar 27, 2014Updated 12 years ago
- Cross compile FPGA tools☆21Jan 4, 2021Updated 5 years ago
- iCE40 floorplan viewer☆24Jun 23, 2018Updated 8 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆41Dec 2, 2018Updated 7 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆74Sep 17, 2026Updated last month
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Test of the USB3 IP Core from Daisho on a Xilinx device☆112Oct 3, 2019Updated 7 years ago
- File editor for the Xilinx AXI Traffic Generator IP☆17Feb 9, 2026Updated 8 months ago
- TLUT tool flow for parameterised configurations for FPGAs☆17Aug 5, 2024Updated 2 years ago
- Wishbone to ARM AMBA 4 AXI☆17May 25, 2019Updated 7 years ago
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆13Jul 14, 2024Updated 2 years ago
- AXI support for Migen/MiSoC☆28Oct 1, 2026Updated 3 weeks ago
- Very small and high performance CPU☆13Dec 3, 2024Updated last year
- Hi-Speed USB (ULPI) interface Pmod™ module for FPGA boards☆10Jan 27, 2017Updated 9 years ago
- A full-speed device-side USB peripheral core written in Verilog.☆244Oct 30, 2022Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- python script to read Agilent (KeySight) oscilloscope binary file☆12Dec 25, 2014Updated 11 years ago
- A Win32 + libusb-1.0 API port of fxload, programming tool for Cypress EZ-USB series.☆10Jun 30, 2015Updated 11 years ago
- Real Digital Vivado IP Library☆10Nov 13, 2022Updated 3 years ago
- LIB:Library for interacting with an FPGA over USB☆86Jan 16, 2021Updated 5 years ago
- Simply Cyclone IV EP4CE10 Developer board (KiCAD edition)☆10Nov 25, 2018Updated 7 years ago
- shdl6800: A 6800 processor written in SpinalHDL☆25Jan 12, 2020Updated 6 years ago
- Sweet32 32bit MRISC CPU - VHDL and software toolchain sources (including documentation)☆39Oct 29, 2015Updated 11 years ago
- ☆19Oct 5, 2020Updated 6 years ago
- An alternative PnR system, or at least an attempt to get it running on Ubuntu 18.04.☆10Aug 31, 2018Updated 8 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ☆15Dec 19, 2025Updated 10 months ago
- VGA demo on bluepill (using STM32F103 microcontroller)☆22Jan 27, 2022Updated 4 years ago
- Enigma in FPGA☆29May 18, 2019Updated 7 years ago
- A circuit board development environment driven by Forth.☆12Dec 12, 2020Updated 5 years ago
- Xilinx JTAG Toolchain on Digilent Arty board☆17Mar 15, 2018Updated 8 years ago
- USB -> AXI Debug Bridge☆47Jun 5, 2021Updated 5 years ago
- Generic Logic Interfacing Project☆49Jul 29, 2020Updated 6 years ago