RClabiisc / I2SRV32-V-v1Links
Reconfigurable Computing Lab, DESE, Indian Institiute of Science
☆32Updated last year
Alternatives and similar repositories for I2SRV32-V-v1
Users that are interested in I2SRV32-V-v1 are comparing it to the libraries listed below
Sorting:
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆29Updated 3 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆17Updated last year
- An 8 input interrupt controller written in Verilog.☆28Updated 13 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- Design and UVM-TB of RISC -V Microprocessor☆33Updated last year
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆51Updated 4 years ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆11Updated last year
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Updated 2 years ago
- North Carolina State University: ECE 745 : Project: LC3 Microcontroller Functional Verification using SystemVerilog☆11Updated 8 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆28Updated 2 months ago
- A 32 point radix-2 FFT module written in Verilog☆25Updated 5 years ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆31Updated 4 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆39Updated last year
- The memory model was leveraged from micron.☆28Updated 7 years ago
- 10 Gigabit Ethernet MAC Core UVM Verification☆16Updated 2 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆27Updated last year
- 128KB AXI cache (32-bit in, 256-bit out)☆55Updated 4 years ago
- ☆41Updated 3 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆78Updated 5 years ago
- ☆33Updated 2 months ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆55Updated 4 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆33Updated 4 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆23Updated 7 years ago
- To design test bench of the APB protocol☆17Updated 5 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆17Updated 2 years ago
- A 2D convolution hardware implementation written in Verilog☆51Updated 5 years ago
- Structured UVM Course☆58Updated 2 years ago
- This repo contain the PY-UVM Framework for different RISC-V Cores☆32Updated 2 years ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆15Updated 2 years ago