Alternatives and similar repositories for I2SRV32-V-v1

Users that are interested in I2SRV32-V-v1 are comparing it to the libraries listed below

• RClabiisc / I2SRV32-S-v1
  Reconfigurable Computing Lab, DESE, Indian Institiute of Science
  ☆29Updated 3 years ago
• martinriis / RISC-V-Vector-Processor
  256-bit vector processor based on the RISC-V vector (V) extension
  ☆31Updated 4 years ago
• RClabiisc / I2SRV64-SS-v1
  Reconfigurable Computing Lab, DESE, Indian Institiute of Science
  ☆27Updated last year
• adibis / Interrupt_Controller
  An 8 input interrupt controller written in Verilog.
  ☆28Updated 13 years ago
• EngAhmed21 / RISC-V-Processor-with-Pipelining
  Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…
  ☆17Updated last year
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆62Updated last year
• BalaDhinesh / Accelerating_Standard_and_Modified_AES128
  Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms
  ☆33Updated 4 years ago
• manili / VSDBabySoC
  VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.
  ☆49Updated 4 years ago
• kumarrishav14 / AMBA_APB
  To design test bench of the APB protocol
  ☆18Updated 5 years ago
• aignacio / nox
  RISC-V Nox core
  ☆71Updated 5 months ago
• alice820621 / SystemVerilog-Implementation-of-DDR3-Controller
  The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…
  ☆22Updated 7 years ago
• mnasser431998 / bfu_dif_fft_rtl
  The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor
  ☆15Updated 2 years ago
• vsdip / vsdsram_sky130
  ☆43Updated 3 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆61Updated 3 years ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆55Updated 4 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆20Updated 2 years ago
• iammituraj / fifo
  Synchronous FIFOs designed in Verilog/System Verilog.
  ☆24Updated 2 weeks ago
• jay16udani / ECE745_LC3_Verification
  North Carolina State University: ECE 745 : Project: LC3 Microcontroller Functional Verification using SystemVerilog
  ☆11Updated 8 years ago
• iammituraj / skid_buffer
  Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
  ☆26Updated 2 months ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆48Updated 3 years ago
• merledu / azadi-soc
  Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.
  ☆32Updated 2 years ago
• Youssefmdany / 10-Gigabit-Ethernet-MAC-Core-UVM-Verification-
  10 Gigabit Ethernet MAC Core UVM Verification
  ☆15Updated 2 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆34Updated 11 months ago
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆47Updated last year
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 3 years ago
• Youssefmdany / Design-and-UVM-TB-of-RISC-V-Microprocessor
  Design and UVM-TB of RISC -V Microprocessor
  ☆32Updated last year
• pulp-platform / axi_llc
  ☆33Updated last month
• tej-chavan / Design-and-Verification-of-DDR3-Memory-Controller
  The memory model was leveraged from micron.
  ☆25Updated 7 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆73Updated last week
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆78Updated 3 years ago