RClabiisc / I2SRV32-V-v1View external linksLinks
Reconfigurable Computing Lab, DESE, Indian Institiute of Science
☆33Jun 22, 2024Updated last year
Alternatives and similar repositories for I2SRV32-V-v1
Users that are interested in I2SRV32-V-v1 are comparing it to the libraries listed below
Sorting:
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆30Jun 27, 2022Updated 3 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆27Jun 22, 2024Updated last year
- ☆15Sep 27, 2022Updated 3 years ago
- IOPMP IP☆22Jul 11, 2025Updated 7 months ago
- PQR5ASM is a RISC-V Assembler compliant with RV32I☆19Apr 18, 2025Updated 9 months ago
- Trying to learn Wishbone by implementing few master/slave devices☆13Jan 7, 2019Updated 7 years ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆11Aug 26, 2024Updated last year
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆13Oct 19, 2024Updated last year
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆39Dec 2, 2018Updated 7 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆29Nov 3, 2025Updated 3 months ago
- North Carolina State University: ECE 745 : Project: LC3 Microcontroller Functional Verification using SystemVerilog☆11Jun 5, 2017Updated 8 years ago
- Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL☆15Mar 21, 2024Updated last year
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Feb 1, 2020Updated 6 years ago
- A collection of URLs related to High Level Synthesis (HLS).☆13Jun 26, 2021Updated 4 years ago
- Original test vector of RISC-V Vector Extension☆14Mar 23, 2021Updated 4 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- Python script for controlling the debug-jtag port of riscv cores☆15Mar 27, 2021Updated 4 years ago
- Input / Output Physical Memory Protection Unit for RISC-V☆15Jul 20, 2023Updated 2 years ago
- Verilog Code for a JPEG Decoder☆34Mar 7, 2018Updated 7 years ago
- RISC-V by VectorBlox☆11Jul 19, 2017Updated 8 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆18Feb 12, 2024Updated 2 years ago
- Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection,…☆16Apr 12, 2020Updated 5 years ago
- Xv6 ports for RISC-V☆15Nov 25, 2024Updated last year
- Simple demo showing how to use the ping pong FIFO☆16May 2, 2016Updated 9 years ago
- A small Neural Network Processor for Edge devices.☆16Nov 22, 2022Updated 3 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆17Sep 2, 2023Updated 2 years ago
- Firmware / software / Verilog for the Photon camera☆14Dec 5, 2025Updated 2 months ago
- ☆36Apr 20, 2021Updated 4 years ago
- 关于深度学习算法、框架、编译器、加速器的一些理解☆16Jul 2, 2022Updated 3 years ago
- Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…☆21Feb 4, 2025Updated last year
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆18Nov 13, 2025Updated 3 months ago
- Matrix Multiplication in Hardware☆16Jun 3, 2020Updated 5 years ago
- xkDLA：XinKai Deep Learning Accelerator (RTL)☆39Jan 15, 2024Updated 2 years ago
- Xilinx JTAG Toolchain on Digilent Arty board☆17Mar 15, 2018Updated 7 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38May 7, 2024Updated last year
- AXI4-Compatible Verilog Cores, along with some helper modules.☆17Mar 14, 2020Updated 5 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆20Jul 29, 2014Updated 11 years ago
- Implementation of an NPU that can be integrated into a RISC- V core through X-Interface.☆34Sep 17, 2024Updated last year