Open FPGA Modules
☆26Oct 8, 2024Updated 2 years ago
Alternatives and similar repositories for ofm
Users that are interested in ofm are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆28Mar 17, 2026Updated 7 months ago
- Testbenches for HDL projects☆23Updated this week
- Network Development Kit (NDK) for FPGA cards with example application☆99Updated this week
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 5 years ago
- An Open Source Link Protocol and Controller☆29Aug 1, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆74Sep 17, 2026Updated last month
- Tensor computing core☆15Jul 8, 2026Updated 3 months ago
- tools regarding on analog modeling, validation, and generation☆25Apr 11, 2023Updated 3 years ago
- ☆18Sep 25, 2026Updated last month
- ☆27Jun 12, 2022Updated 4 years ago
- Verilog PreProcessor.☆12Nov 9, 2015Updated 10 years ago
- BaseJump Open-Source Hardware Accelerator Packages and Sockets☆12Jul 7, 2025Updated last year
- WaveEye is an AXI4-Lite protocol root cause analysis tool that explains why a violation must occur by identifying missing inter-FSM depen…☆13Mar 30, 2026Updated 6 months ago
- RTL and UVM test code of a Multi-NoC system☆12Dec 7, 2021Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- This repo contains the scripts that are used to model and optimize an optical receiver.☆12Jun 4, 2024Updated 2 years ago
- Open source FPGA-based NIC and platform for in-network compute☆71Aug 21, 2025Updated last year
- ☆10Nov 2, 2023Updated 2 years ago
- Create database files for the genealogytree LaTeX package from GEDCOM files☆11Sep 21, 2026Updated last month
- The UVM written in Python☆18Updated this week
- SoC based on RISC V ISA☆10Apr 22, 2022Updated 4 years ago
- SISO vector decoder for IRA-LDPC codes in VHDL☆12Oct 18, 2022Updated 4 years ago
- Secure and Fast FPGA-based Hardware Scheduler for Accelerating Task Scheduling in Multi-core Systems☆13Apr 25, 2023Updated 3 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆14Nov 9, 2015Updated 10 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Large-scale 2D mesh system with dedicated GeMM, on-chip RDMA and Rendez-vous accelerators.☆29Updated this week
- Wake build descriptions of hardware generators☆12Dec 11, 2020Updated 5 years ago
- courses to learn VHDL☆16Mar 14, 2022Updated 4 years ago
- Testbed for testing NetFlow/IPFIX network monitoring probes. Includes tools for PCAP generation and replay of 1/10/100G network traffic.☆60Sep 23, 2026Updated last month
- VHDL implementation of carrier phase recovery (CPR) techniques for coherent optical systems☆16Dec 6, 2020Updated 5 years ago
- USB-PD-3.1-Verilog☆17Apr 22, 2024Updated 2 years ago
- SystemVerilog code for image processing tasks like demosaicing☆11Jun 28, 2020Updated 6 years ago
- Open Source Verification Bundle for VHDL and System Verilog☆48Jan 12, 2024Updated 2 years ago
- Open source Photonics PDK for VTT's 3 um SOI platform.☆16Sep 16, 2026Updated last month
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- This is a Vivado project to create an IoT device with ZYBO (Zynq).☆13Jan 18, 2018Updated 8 years ago
- UVM components for DSP tasks (MODulation/DEModulation)☆16Mar 2, 2022Updated 4 years ago
- Verilog-Based-NoC-Simulator☆12May 4, 2016Updated 10 years ago
- SystemVerilog derslerinde yazdığım kodları içermektedir.☆15Nov 19, 2023Updated 2 years ago
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆12Sep 23, 2022Updated 4 years ago
- Heston implementation for Zynq with Vivado HLS☆16Jun 30, 2015Updated 11 years ago
- ESnet general-purpose FPGA design library.☆14Oct 21, 2026Updated last week