CESNET / ofmLinks
Open FPGA Modules
☆23Updated 8 months ago
Alternatives and similar repositories for ofm
Users that are interested in ofm are comparing it to the libraries listed below
Sorting:
- UART models for cocotb☆29Updated 2 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- ☆59Updated 3 years ago
- Hamming ECC Encoder and Decoder to protect memories☆33Updated 4 months ago
- SystemVerilog Linter based on pyslang☆31Updated last month
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆48Updated last year
- Python Tool for UVM Testbench Generation☆53Updated last year
- A simple DDR3 memory controller☆55Updated 2 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Updated 5 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆70Updated 9 months ago
- SGMII☆12Updated 10 years ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆14Updated 6 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- I2C models for cocotb☆35Updated 3 months ago
- ☆32Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 6 months ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆31Updated 3 weeks ago
- This repo contain the PY-UVM Framework for different RISC-V Cores☆31Updated last year
- 1000BASE-X IEEE 802.3-2008 Clause 36 - Physical Coding Sublayer (PCS)☆20Updated 10 years ago
- Open Source Verification Bundle for VHDL and System Verilog☆45Updated last year
- Generic FIFO implementation with optional FWFT☆58Updated 5 years ago
- APB UVC ported to Verilator☆11Updated last year
- Verilog HDL implementation of SDRAM controller and SDRAM model☆27Updated last year
- OSVVM Documentation☆34Updated this week
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆33Updated 4 months ago
- ☆30Updated 2 months ago
- ☆18Updated 8 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated last year
- ☆20Updated 5 years ago