Alternatives and similar repositories for ROUTER-1-3:

Users that are interested in ROUTER-1-3 are comparing it to the libraries listed below

• srishis / DMA8237A_VERIF
  Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench
  ☆11Updated 4 years ago
• deekshithkrishnegowda / AHB2APB-bridge-IP-core-verification
  Maven Silicon Project
  ☆17Updated 6 years ago
• Anjali-287 / Synchronous-FIFO-UVM-TB
  UVM Testbench for synchronus fifo
  ☆17Updated 4 years ago
• raiyyanfaisal09 / Router1X3_RTL_Design
  - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…
  ☆10Updated 5 years ago
• Artityagi123456789 / -100dasofSystemVerilog
  System Verilog using Functional Verification
  ☆10Updated last year
• forever-gk / AHB-SystemVerilog
  ☆17Updated 10 years ago
• vritrv / ROUTER-1X3-RTL-DESIGN
  Architectural design of data router in verilog
  ☆29Updated 5 years ago
• canbozaci / Cache
  L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC
  ☆11Updated 2 years ago
• mayurkubavat / SystemVerilog
  SystemVerilog examples and projects
  ☆17Updated 6 years ago
• emmanouil-komninos / jtag_vip_uvm
  ☆12Updated 9 years ago
• Gateway91 / AHB-APB_Bridge_UVM_Env
  AHB-APB UVM Verification Environment
  ☆18Updated 9 years ago
• marshall-999 / UVMReference
  This is a open source project from UVM Community and it is based on an Ethernet Switch System-on-Chip (SoC).
  ☆13Updated 3 years ago
• Vivek-Dave / UVM_TestBench_For_Single_Port_RAM
  A complete UVM TB for verification of single port 64KB RAM
  ☆15Updated 4 years ago
• wanderingnail / AXI_DMA
  ☆19Updated 2 years ago
• kumarrishav14 / AMBA_APB
  To design test bench of the APB protocol
  ☆17Updated 4 years ago
• letitbe0201 / AXI-DMA-master-verification
  ☆25Updated 3 years ago
• wbbbbbb123 / UVM-based-AHB-bus-SRAM-controller-design-verification-platform-design
  ☆14Updated 2 years ago
• xdesigns / 4way-cache
  Verilog cache implementation of 4-way FIFO 16k Cache
  ☆19Updated 12 years ago
• fighter212 / ahb2apb
  this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.
  ☆16Updated 10 years ago
• EngAhmed21 / RISC-V-Processor-with-Pipelining
  Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…
  ☆14Updated last year
• techvinodreddy / UART-IP-CORE16550A-Verification-UVM
  The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …
  ☆17Updated 3 years ago
• Ghonimo / Pre_Silicon-AHB-to_APB-Verification
  Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀
  ☆25Updated last year
• wenxuan-hu / SSRL_work
  work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
  ☆31Updated 2 years ago
• yvnr4you / SDRAM-Verification
  This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …
  ☆25Updated 8 years ago
• nguyenquanicd / AllArbiterRTLCode
  RTL code of some arbitration algorithm
  ☆14Updated 5 years ago
• Youssefmdany / Design-and-UVM-TB-of-RISC-V-Microprocessor
  Design and UVM-TB of RISC -V Microprocessor
  ☆18Updated 10 months ago
• muguang123 / AXI_Verification
  Verification AXI-4 bus standard using UVM and System Verilog
  ☆15Updated 7 years ago
• smartfoxdata / uvm_axi4lite
  uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol
  ☆22Updated 3 months ago
• kkenshin1 / AXI-Ethernet-UVM
  A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM
  ☆25Updated 2 years ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 5 years ago