Alternatives and similar repositories for daisho

Users that are interested in daisho are comparing it to the libraries listed below

• ECP5-PCIe / ECP5-PCIe
  Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe
  ☆102Updated 2 years ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆94Updated 5 years ago
• ZipCPU / wbscope
  A wishbone controlled scope for FPGA's
  ☆84Updated last year
• quartiq / bscan_spi_bitstreams
  FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.
  ☆56Updated 2 years ago
• ultraembedded / core_usb_cdc
  Basic USB-CDC device core (Verilog)
  ☆80Updated 4 years ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆95Updated 5 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆68Updated last month
• im-tomu / valentyusb
  FPGA USB stack written in LiteX
  ☆129Updated 3 years ago
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆71Updated 3 years ago
• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆80Updated 3 years ago
• j-marjanovic / jtag-quartus-ft232h
  ☆53Updated 3 years ago
• enjoy-digital / usb3_pipe
  USB3 PIPE interface for Xilinx 7-Series
  ☆234Updated 3 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆49Updated 2 weeks ago
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆91Updated 7 years ago
• BerkeleyLab / XVC-FTDI-JTAG
  Xilinx virtual cable server for generic FTDI 4232H.
  ☆59Updated last year
• ultraembedded / core_usb_uart
  USB serial device (CDC-ACM)
  ☆41Updated 5 years ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆46Updated 5 years ago
• brouhaha / xchange
  Change part number or package in a Xilinx 7-series FPGA bitstream
  ☆41Updated 5 years ago
• alexforencich / pin-uart
  FPGA board-level debugging and reverse-engineering tool
  ☆38Updated 2 years ago
• ulixxe / usb_cdc
  Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs
  ☆181Updated last year
• no2fpga / no2usb
  Nitro USB FPGA core
  ☆86Updated last year
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆52Updated 2 years ago
• esynr3z / usb20dev
  USB 2.0 FS Device controller IP core written in SystemVerilog
  ☆37Updated 6 years ago
• ZipCPU / fftdemo
  A demonstration showing how several components can be compsed to build a simulated spectrogram
  ☆46Updated last year
• pbing / USB
  FPGA USB 1.1 Low-Speed Implementation
  ☆34Updated 7 years ago
• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆181Updated 2 weeks ago
• sparrowgrine / prjtritium
  ☆22Updated 3 years ago
• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆67Updated 9 months ago
• j-marjanovic / ocs-tray-mezzanine-adapter
  PCIe adapter for an FPGA accelerator for Open CloudServer
  ☆24Updated 5 years ago