freecores / axi_master
Generic AXI master stub
☆19Updated 10 years ago
Related projects ⓘ
Alternatives and complementary repositories for axi_master
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- Generic AXI to APB bridge☆12Updated 10 years ago
- ☆20Updated 5 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆26Updated last year
- DDR3 SDRAM controller☆18Updated 10 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- Implementation of the PCIe physical layer☆30Updated last week
- Hamming ECC Encoder and Decoder to protect memories☆28Updated last month
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆29Updated 6 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆17Updated 6 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 3 years ago
- WISHBONE Interconnect☆11Updated 7 years ago
- SoC Based on ARM Cortex-M3☆25Updated 6 months ago
- verification of simple axi-based cache☆17Updated 5 years ago
- ☆16Updated 5 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆25Updated 3 weeks ago
- JTAG DPI module for SystemVerilog RTL simulations☆26Updated 9 years ago
- Direct Access Memory for MPSoC☆12Updated 3 weeks ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- A Verilog AMBA AHB Multilayer interconnect generator☆12Updated 7 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆17Updated 5 years ago
- Andes Vector Extension support added to riscv-dv☆14Updated 4 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 6 years ago
- The memory model was leveraged from micron.☆19Updated 6 years ago
- ☆33Updated 2 years ago
- General Purpose AXI Direct Memory Access☆44Updated 6 months ago
- Reed Solomon Decoder (204,188)☆11Updated 10 years ago
- AHB Bus lite v3.0☆13Updated 5 years ago
- A Verilog implementation of a processor cache.☆19Updated 6 years ago