USB 1.1 Host and Function IP core
☆27Jul 17, 2014Updated 12 years ago
Alternatives and similar repositories for usbhostslave
Users that are interested in usbhostslave are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- USB 2.0 Device IP Core☆76Oct 1, 2017Updated 9 years ago
- USB1.1 Host Controller + PHY☆18Aug 4, 2021Updated 5 years ago
- MMU for Z80 and eZ80☆21Mar 4, 2021Updated 5 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆41Dec 2, 2018Updated 7 years ago
- ☆13Nov 5, 2017Updated 8 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Ethernet MAC 10/100 Mbps☆39Oct 31, 2021Updated 4 years ago
- PS2 interface☆18Dec 4, 2017Updated 8 years ago
- ULA chip for ZX Spectrum☆23Jul 17, 2014Updated 12 years ago
- Single RISC-V CPU attached on AMBA AHB with Instruction and Data memories.☆13Apr 18, 2026Updated 5 months ago
- DDR3 SDRAM controller☆18Jul 17, 2014Updated 12 years ago
- FPGA implementation of a simple scanline based 2d graphics engine☆25Feb 26, 2019Updated 7 years ago
- Ethernet MAC 10/100 Mbps☆90Oct 2, 2019Updated 7 years ago
- A collection of SPI related cores☆23Nov 12, 2024Updated last year
- WISHBONE Interconnect☆11Oct 1, 2017Updated 9 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆14Jun 30, 2019Updated 7 years ago
- A dedicated graphical processor for ray tracing☆22Jun 7, 2021Updated 5 years ago
- USB 1.1 PHY☆12Jul 17, 2014Updated 12 years ago
- Systolic Array implementation for ASIC Course☆15Nov 26, 2023Updated 2 years ago
- 《自己动手写编译器、链接器》的前5章的linux实现☆11Feb 9, 2021Updated 5 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆22Nov 21, 2017Updated 8 years ago
- ☆29Oct 20, 2019Updated 6 years ago
- RISC CPU by Icenowy☆12Dec 26, 2018Updated 7 years ago
- SPI interface connect to APB BUS with Verilog HDL☆43Jun 27, 2021Updated 5 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Basic USB 1.1 Host Controller for small FPGAs☆103Jun 6, 2020Updated 6 years ago
- 8051 core☆118Jul 17, 2014Updated 12 years ago
- Basic USB-CDC device core (Verilog)☆94May 15, 2021Updated 5 years ago
- My notes on various programming languages and CS concepts☆16Dec 8, 2022Updated 3 years ago
- 74HCT6526☆14Nov 8, 2023Updated 2 years ago
- DUTH RISC-V Superscalar Microprocessor☆35Oct 23, 2024Updated last year
- USB -> AXI Debug Bridge☆47Jun 5, 2021Updated 5 years ago
- riscv uclinux☆15Aug 9, 2019Updated 7 years ago
- A complete 65C02 computer with VGA output on a Lattice Ultra Plus FPGA☆29Jun 12, 2019Updated 7 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- sn76489an compatible Verilog core, with emphasis on FPGA implementation and Megadrive/Master System compatibility☆34Jan 6, 2025Updated last year
- Test dashboard for verification features in Verilator☆35Updated this week
- Test of the USB3 IP Core from Daisho on a Xilinx device☆111Oct 3, 2019Updated 7 years ago
- USB2.0 Verilog☆20Apr 21, 2019Updated 7 years ago
- Mega/Xmega soft core RTL design.☆11Feb 21, 2020Updated 6 years ago
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆19Dec 12, 2025Updated 10 months ago
- e300 and u500 devkits☆10Nov 15, 2020Updated 5 years ago