USB 1.1 Host and Function IP core
☆26Jul 17, 2014Updated 11 years ago
Alternatives and similar repositories for usbhostslave
Users that are interested in usbhostslave are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- USB1.1 Host Controller + PHY☆15Aug 4, 2021Updated 4 years ago
- USB 2.0 Device IP Core☆75Oct 1, 2017Updated 8 years ago
- USB2.0 Device Controller IP Core☆16Aug 18, 2023Updated 2 years ago
- MMU for Z80 and eZ80☆21Mar 4, 2021Updated 5 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆41Dec 2, 2018Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆14Nov 5, 2017Updated 8 years ago
- A collection of SPI related cores☆21Nov 12, 2024Updated last year
- PS2 interface☆18Dec 4, 2017Updated 8 years ago
- Ethernet MAC 10/100 Mbps☆37Oct 31, 2021Updated 4 years ago
- DDR3 SDRAM controller☆18Jul 17, 2014Updated 11 years ago
- Platform Level Interrupt Controller☆47May 10, 2024Updated last year
- FPGA implementation of a simple scanline based 2d graphics engine☆24Feb 26, 2019Updated 7 years ago
- Ethernet MAC 10/100 Mbps☆86Oct 2, 2019Updated 6 years ago
- USB 1.1 Device IP Core☆21Oct 1, 2017Updated 8 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- WISHBONE Interconnect☆11Oct 1, 2017Updated 8 years ago
- ☆14Jun 30, 2019Updated 6 years ago
- USB 1.1 PHY☆11Jul 17, 2014Updated 11 years ago
- A dedicated graphical processor for ray tracing☆22Jun 7, 2021Updated 4 years ago
- Single RISC-V CPU attached on AMBA AHB with Instruction and Data memories.☆13Apr 18, 2026Updated 2 weeks ago
- Theia: ray graphic processing unit☆20Jul 17, 2014Updated 11 years ago
- 《自己动手写编译器、链接器》的前5章的linux实现☆11Feb 9, 2021Updated 5 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆22Nov 21, 2017Updated 8 years ago
- ☆29Oct 20, 2019Updated 6 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- RISC CPU by Icenowy☆12Dec 26, 2018Updated 7 years ago
- 8051 core☆112Jul 17, 2014Updated 11 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆99Jun 6, 2020Updated 5 years ago
- DUTH RISC-V Superscalar Microprocessor☆35Oct 23, 2024Updated last year
- riscv uclinux☆15Aug 9, 2019Updated 6 years ago
- Basic USB-CDC device core (Verilog)☆89May 15, 2021Updated 4 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆31Jan 6, 2020Updated 6 years ago
- SPI interface connect to APB BUS with Verilog HDL☆41Jun 27, 2021Updated 4 years ago
- 74HCT6526☆14Nov 8, 2023Updated 2 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- My notes on various programming languages and CS concepts☆16Dec 8, 2022Updated 3 years ago
- HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-sla…☆26Mar 5, 2025Updated last year
- Superscalar Out-of-Order NPU Design on FPGA☆14May 17, 2024Updated last year
- sn76489an compatible Verilog core, with emphasis on FPGA implementation and Megadrive/Master System compatibility☆31Jan 6, 2025Updated last year
- Test of the USB3 IP Core from Daisho on a Xilinx device☆104Oct 3, 2019Updated 6 years ago
- A complete 65C02 computer with VGA output on a Lattice Ultra Plus FPGA☆29Jun 12, 2019Updated 6 years ago
- USB -> AXI Debug Bridge☆44Jun 5, 2021Updated 4 years ago