freecores / usbhostslaveLinks
USB 1.1 Host and Function IP core
☆23Updated 10 years ago
Alternatives and similar repositories for usbhostslave
Users that are interested in usbhostslave are comparing it to the libraries listed below
Sorting:
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- SPI-Flash XIP Interface (Verilog)☆38Updated 3 years ago
- PCI bridge☆18Updated 10 years ago
- USB Full Speed PHY☆44Updated 5 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆36Updated 6 years ago
- turbo 8051☆29Updated 7 years ago
- DDR3 SDRAM controller☆18Updated 10 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆33Updated 5 years ago
- Wishbone interconnect utilities☆41Updated 4 months ago
- Verilog Repository for GIT☆33Updated 4 years ago
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆27Updated 6 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 4 years ago
- AHB-Lite Quad I/O SPI Flash memory controller with direct mapped cache and support for XiP☆12Updated last year
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- UART 16550 core☆37Updated 10 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆20Updated 5 years ago
- USB -> AXI Debug Bridge☆39Updated 4 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- Small (Q)SPI flash memory programmer in Verilog☆63Updated 2 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆22Updated 7 years ago
- JTAG Test Access Port (TAP)☆34Updated 10 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆64Updated 5 years ago
- It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.☆17Updated 5 years ago
- Sata 2 Host Controller for FPGA implementation☆17Updated 7 years ago
- AXI-4 RAM Tester Component☆17Updated 4 years ago
- USB 2.0 Device IP Core☆68Updated 7 years ago
- Generic AXI master stub☆19Updated 10 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆79Updated last year