Verification IP for UART protocol
☆25Aug 3, 2020Updated 5 years ago
Alternatives and similar repositories for uart_vip
Users that are interested in uart_vip are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verification IP for SPI protocol☆21Jul 23, 2020Updated 5 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆14Nov 9, 2015Updated 10 years ago
- Verification IP for I2C protocol☆52Sep 22, 2021Updated 4 years ago
- Verification IP for APB protocol☆34Sep 9, 2020Updated 5 years ago
- Universal Asynchronous Receiver/Transmitter (UART) with FIFOs Soft IP☆15Feb 18, 2025Updated last year
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- APB VIP (UVM)☆18Sep 6, 2018Updated 7 years ago
- ☆26May 31, 2021Updated 4 years ago
- SPI protocol Accelerated VIP☆27Apr 21, 2022Updated 4 years ago
- EasierUVM from Doulos now written in Python for easier UVM with framework and template generator☆13Sep 28, 2022Updated 3 years ago
- ☆50Nov 3, 2023Updated 2 years ago
- ☆29May 11, 2021Updated 5 years ago
- ☆14Nov 11, 2015Updated 10 years ago
- ☆12May 31, 2016Updated 9 years ago
- ☆22May 18, 2018Updated 8 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆17Jun 24, 2020Updated 5 years ago
- Verification IP for Watchdog☆13Apr 6, 2021Updated 5 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆15Mar 26, 2024Updated 2 years ago
- To verify the SPI Master IP using the APB and SPI AVIPs☆22Apr 21, 2022Updated 4 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Dec 26, 2022Updated 3 years ago
- Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation inc…☆35Mar 23, 2024Updated 2 years ago
- ☆15May 10, 2019Updated 7 years ago
- ☆14Nov 5, 2017Updated 8 years ago
- The memory model was leveraged from micron.☆30Mar 24, 2018Updated 8 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Verification IP for APB protocol☆77Dec 18, 2020Updated 5 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆21Dec 8, 2012Updated 13 years ago
- UVM Testbench for synchronus fifo☆19Aug 28, 2020Updated 5 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆26Mar 8, 2026Updated 2 months ago
- Vivado project for Xilinx Artix FPGA, used in logic analyzer☆14Jul 16, 2021Updated 4 years ago
- UART design in SV and verification using UVM and SV☆58Nov 30, 2019Updated 6 years ago
- RISCV CPU implementation in SystemVerilog☆32Mar 17, 2026Updated 2 months ago
- Maven Silicon Project☆19Oct 13, 2018Updated 7 years ago
- ☆12May 8, 2022Updated 4 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- WISHBONE Interconnect☆11Oct 1, 2017Updated 8 years ago
- AMBA 3 AHB UVM TB☆35Mar 21, 2019Updated 7 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- 8b/10b is a line code that maps 8-bit words to 10-bit symbols to achieve DC-balance and bounded disparity, which is used for telecommunic…☆12Jun 8, 2021Updated 4 years ago
- USB 1.1 PHY☆11Jul 17, 2014Updated 11 years ago
- Generic AHB master stub☆12Jul 17, 2014Updated 11 years ago
- This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.☆49Jun 19, 2020Updated 5 years ago