Alternatives and similar repositories for axi-dma-controller

Users that are interested in axi-dma-controller are comparing it to the libraries listed below

• Aquaticfuller / OpenExSys_NoC
  OpenExSys_NoC a mesh-based network on chip IP.
  ☆18Updated last year
• tom-urkin / AMBA
  AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog
  ☆16Updated 2 years ago
• CospanDesign / verilog_ppfifo_demo
  Simple demo showing how to use the ping pong FIFO
  ☆15Updated 9 years ago
• vfinotti / ahb3lite_dma
  DMA core compatible with AHB3-Lite
  ☆10Updated 6 years ago
• ZipCPU / axidmacheck
  AXI DMA Check: A utility to measure DMA speeds in simulation
  ☆15Updated 9 months ago
• pulp-platform / hier-icache
  ☆13Updated 8 months ago
• iammituraj / skid_buffer
  Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
  ☆26Updated this week
• Verdvana / Async_FIFO
  位宽和深度可定制的异步FIFO
  ☆13Updated last year
• open-dv / dma_axi
  ☆16Updated 6 years ago
• pulp-platform / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆18Updated 3 months ago
• jiayi-wang98 / lpddr4_memory_controller
  ☆10Updated 3 years ago
• fighter212 / ahb2apb
  this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.
  ☆18Updated 11 years ago
• haifengch / axi_interconnect
  ☆26Updated 4 months ago
• ultraembedded / core_jpeg_decoder
  HW JPEG decoder wrapper with AXI-4 DMA
  ☆36Updated 5 years ago
• aignacio / ahb_lite_bus
  AHB Bus lite v3.0
  ☆16Updated 6 years ago
• trivedidvijen / SPI-to-I2C-Protocol-Conversion-Using-Verilog
  SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.
  ☆11Updated 4 years ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 6 years ago
• pulp-platform / redundancy_cells
  SystemVerilog IPs and Modules for architectural redundancy designs.
  ☆14Updated 2 weeks ago
• srohit0 / CORDIC
  CORDIC VLSI-IP for deep learning activation functions
  ☆15Updated 6 years ago
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆16Updated 5 years ago
• dpretet / bster
  Implementation of a binary search tree algorithm in a FPGA/ASIC IP
  ☆20Updated 4 years ago
• Purdue-SoCET / atalla
  Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.
  ☆18Updated last week
• GuiZhaoCodeSource / Func_Verif_MMU_Code_Source
  Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache
  ☆13Updated 10 years ago
• yuhsuan-t / NPU-Architecture
  CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations
  ☆19Updated 8 years ago
• pulp-platform / axi_llc
  ☆30Updated 2 weeks ago
• CMU-SAFARI / MIG-7-PHY-DDR3-Controller
  A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.
  ☆11Updated 4 years ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆32Updated 9 years ago
• fpgasystems / groundhog
  Groundhog - Serial ATA Host Bus Adapter
  ☆24Updated 7 years ago
• PacoReinaCampo / MPSoC-DMA
  Direct Access Memory for MPSoC
  ☆13Updated 5 months ago
• wanderingnail / AXI_DMA
  ☆20Updated 2 years ago