enjoy-digital / litejesd204bLinks
Small footprint and configurable JESD204B core
☆50Updated 2 months ago
Alternatives and similar repositories for litejesd204b
Users that are interested in litejesd204b are comparing it to the libraries listed below
Sorting:
- Extensible FPGA control platform☆61Updated 2 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆106Updated this week
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆69Updated 3 weeks ago
- Small footprint and configurable Inter-Chip communication cores☆66Updated 2 months ago
- JESD204B core for Migen/MiSoC☆35Updated 4 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆32Updated 3 years ago
- This repository contains synthesizable examples which use the PoC-Library.☆39Updated 5 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆97Updated 5 years ago
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆32Updated 8 years ago
- Wishbone to AXI bridge (VHDL)☆44Updated 6 years ago
- Generic Logic Interfacing Project☆48Updated 5 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆46Updated this week
- Project X-Ray Database: XC7 Series☆73Updated 4 years ago
- Xilinx virtual cable server for generic FTDI 4232H.☆59Updated last year
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆39Updated 10 months ago
- Test of the USB3 IP Core from Daisho on a Xilinx device☆100Updated 6 years ago
- ☆30Updated 4 years ago
- Verilog FT245 to AXI stream interface☆29Updated 7 years ago
- Library of reusable VHDL components☆28Updated last year
- USB Full Speed PHY☆48Updated 5 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆46Updated 10 years ago
- Altium Designer libraries for ANSI/VITA 57 FPGA Mezzanine Card (FMC) Standard☆45Updated 4 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated 2 years ago
- JESD204b modules in VHDL☆30Updated 6 years ago
- Small footprint and configurable SPI core☆46Updated last month
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆53Updated 2 years ago
- Spen's Official OpenOCD Mirror☆51Updated 10 months ago
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- VHDL PCIe Transceiver☆32Updated 5 years ago
- PicoRV☆43Updated 5 years ago