ananthbhat94 / DDR4MemoryControllerLinks
HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
☆75Updated 7 years ago
Alternatives and similar repositories for DDR4MemoryController
Users that are interested in DDR4MemoryController are comparing it to the libraries listed below
Sorting:
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- AMBA bus generator including AXI, AHB, and APB☆102Updated 3 years ago
- An AXI4 crossbar implementation in SystemVerilog☆157Updated last week
- AXI DMA 32 / 64 bits☆113Updated 10 years ago
- round robin arbiter☆74Updated 10 years ago
- General Purpose AXI Direct Memory Access☆51Updated last year
- Generic FIFO implementation with optional FWFT☆58Updated 5 years ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- ☆55Updated 2 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆126Updated 7 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆33Updated 2 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆56Updated last year
- ☆34Updated 6 years ago
- SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core☆143Updated 6 years ago
- Network on Chip Implementation written in SytemVerilog☆178Updated 2 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆60Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆57Updated this week
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- ☆59Updated 4 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- This is the repository for the IEEE version of the book☆66Updated 4 years ago
- AXI总线连接器☆99Updated 5 years ago
- AHB DMA 32 / 64 bits☆56Updated 10 years ago
- amba3 apb/axi vip☆50Updated 10 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆166Updated 7 months ago
- DDR2 memory controller written in Verilog☆77Updated 13 years ago
- SDRAM controller with AXI4 interface☆94Updated 5 years ago
- AXI Interconnect☆49Updated 3 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆101Updated last year