ananthbhat94 / DDR4MemoryController
HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
☆74Updated 7 years ago
Alternatives and similar repositories for DDR4MemoryController
Users that are interested in DDR4MemoryController are comparing it to the libraries listed below
Sorting:
- AMBA bus generator including AXI, AHB, and APB☆100Updated 3 years ago
- An AXI4 crossbar implementation in SystemVerilog☆148Updated this week
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- AXI DMA 32 / 64 bits☆113Updated 10 years ago
- General Purpose AXI Direct Memory Access☆49Updated last year
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- round robin arbiter☆73Updated 10 years ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- AXI总线连接器☆97Updated 5 years ago
- DDR2 memory controller written in Verilog☆78Updated 13 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- ☆51Updated 2 years ago
- SDRAM controller with AXI4 interface☆92Updated 5 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆60Updated 4 years ago
- SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core☆141Updated 6 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- Generic FIFO implementation with optional FWFT☆57Updated 4 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆96Updated last year
- This is the repository for the IEEE version of the book☆58Updated 4 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆126Updated 7 years ago
- ☆62Updated 9 years ago
- Network on Chip Implementation written in SytemVerilog☆174Updated 2 years ago
- ☆33Updated 6 years ago
- PCIE 5.0 Graduation project (Verification Team)☆70Updated last year
- AXI Interconnect☆49Updated 3 years ago
- ☆75Updated 10 years ago
- AHB DMA 32 / 64 bits☆54Updated 10 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆40Updated 3 years ago
- ☆56Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆56Updated 2 months ago