Alternatives and similar repositories for wb_builder

Users that are interested in wb_builder are comparing it to the libraries listed below

• freecores / wdsp
  DSP WishBone Compatible Cores
  ☆14Updated 11 years ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆28Updated 4 years ago
• rbarzic / nanorv32
  A small 32-bit implementation of the RISC-V architecture
  ☆32Updated 5 years ago
• Paebbels / PicoBlaze-Library
  The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…
  ☆36Updated 4 years ago
• ultraembedded / cortex_m0_wrapper
  Cortex-M0 DesignStart Wrapper
  ☆21Updated 6 years ago
• jeras / fpga-hdl
  A set of small Verilog projects, to simulate and implement on FPGA development boards
  ☆15Updated 7 years ago
• mcci-catena / catena-riscv32-fpga
  RISC-V 32-bit core for MCCI Catena 4710
  ☆10Updated 6 years ago
• freecores / turbo8051
  turbo 8051
  ☆29Updated 8 years ago
• edaplayground / epwave
  EPWave -- The Free Interactive Browser-Based Wave Viewer
  ☆14Updated 10 years ago
• bwitherspoon / rv32cpu
  A RISC-V processor
  ☆15Updated 6 years ago
• freecores / usbhostslave
  USB 1.1 Host and Function IP core
  ☆24Updated 11 years ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆47Updated 5 years ago
• freecores / usb_phy
  USB 1.1 PHY
  ☆11Updated 11 years ago
• efabless / caravel-lite
  ☆17Updated last year
• TUT-ASI / leon3-grlib-gpl-mirror
  Automated Git mirror of Gaisler's GRLIB/Leon3 releases
  ☆20Updated 2 weeks ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆52Updated 2 years ago
• open-design / riscv-soc-cores
  ☆40Updated 4 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆66Updated last month
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆23Updated last year
• stnolting / cjtag_bridge
  🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.
  ☆25Updated 3 years ago
• qermit / WishboneAXI
  Wishbone to AXI bridge (VHDL)
  ☆43Updated 6 years ago
• taichi-ishitani / rggen
  This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
  ☆17Updated 6 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆21Updated 2 years ago
• www-asics-ws / usb1_device
  USB 1.1 Device IP Core
  ☆21Updated 8 years ago
• umarcor / hwstudio
  GUI editor for hardware description designs
  ☆30Updated 2 years ago
• cloudxcc / Arduissimo
  Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).
  ☆21Updated 5 years ago
• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 11 years ago
• freecores / sc2v
  SystemC to Verilog Synthesizable Subset Translator
  ☆12Updated 2 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆43Updated 9 months ago