Alternatives and similar repositories for wb_builder:

Users that are interested in wb_builder are comparing it to the libraries listed below

• freecores / wdsp
  DSP WishBone Compatible Cores
  ☆13Updated 10 years ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆25Updated 3 years ago
• jeras / fpga-hdl
  A set of small Verilog projects, to simulate and implement on FPGA development boards
  ☆13Updated 6 years ago
• Paebbels / PicoBlaze-Library
  The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…
  ☆35Updated 4 years ago
• pliu6 / vhd2vl
  vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.
  ☆26Updated 9 years ago
• Digilent / Arty-A7-35-XADC
  ☆18Updated 4 years ago
• rbarzic / nanorv32
  A small 32-bit implementation of the RISC-V architecture
  ☆32Updated 4 years ago
• freecores / sc2v
  SystemC to Verilog Synthesizable Subset Translator
  ☆9Updated last year
• ultraembedded / core_ulpi_wrapper
  ULPI Link Wrapper (USB Phy Interface)
  ☆25Updated 4 years ago
• stnolting / cjtag_bridge
  🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.
  ☆23Updated 3 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆37Updated 3 years ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆41Updated 4 years ago
• freecores / usbhostslave
  USB 1.1 Host and Function IP core
  ☆20Updated 10 years ago
• lawrie / tiny_ram_soc
  Picorv32 SoC that uses only BRAM, not flash memory
  ☆12Updated 6 years ago
• freecores / turbo8051
  turbo 8051
  ☆28Updated 7 years ago
• esynr3z / usb20dev
  USB 2.0 FS Device controller IP core written in SystemVerilog
  ☆34Updated 6 years ago
• hdl-util / i2c
  Fully featured implementation of Inter-IC (I2C) bus master for FPGAs
  ☆26Updated 4 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆38Updated 3 weeks ago
• ZipCPU / wbspi
  A collection of SPI related cores
  ☆15Updated 3 months ago
• michg / pyocdriscv32
  Python script for controlling the debug-jtag port of riscv cores
  ☆14Updated 3 years ago
• freecores / embedded_risc
  Embedded 32-bit RISC uProcessor with SDRAM Controller
  ☆25Updated 3 years ago
• freecores / wb_dma
  WISHBONE DMA/Bridge IP Core
  ☆18Updated 10 years ago
• freecores / pci
  PCI bridge
  ☆18Updated 10 years ago
• paulscherrerinstitute / xvcSupport
  ☆17Updated 4 years ago
• TUT-ASI / leon3-grlib-gpl-mirror
  Automated Git mirror of Gaisler's GRLIB/Leon3 releases
  ☆17Updated 2 months ago
• KutuSystems / XilinxIP
  Xilinx IP repository
  ☆13Updated 6 years ago
• Wren6991 / HyperRam
  simple hyperram controller
  ☆11Updated 6 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆22Updated last year
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆29Updated 2 months ago