Example Codes for Snorkeling in Verilog Bay
☆17Sep 9, 2016Updated 9 years ago
Alternatives and similar repositories for Example-Codes-for-Snorkeling-in-Verilog-Bay
Users that are interested in Example-Codes-for-Snorkeling-in-Verilog-Bay are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- unsigned Radix-2 SRT division,基2除法☆17May 12, 2015Updated 11 years ago
- a multiplier÷r verilog RTL file for RV32M instructions☆14Mar 17, 2020Updated 6 years ago
- ASIC Design of the openSPARC Floating Point Unit☆17Mar 13, 2017Updated 9 years ago
- There are the documents, floating and fixed-point algorithms, and Verilog codes for the project.☆11Jun 27, 2016Updated 10 years ago
- Automatically exported from code.google.com/p/asy4cn☆11Jul 11, 2022Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆11Jun 6, 2021Updated 5 years ago
- Collection of examples for the MiniSat API☆16Feb 1, 2011Updated 15 years ago
- fpga i2c slave verilog hdl rtl☆16Nov 26, 2015Updated 10 years ago
- ☆19Aug 10, 2020Updated 6 years ago
- An attempt to synthesize GPS signals in FPGA logic.☆19Feb 17, 2026Updated 6 months ago
- Gaussian noise generator Verilog IP core☆34Jul 5, 2026Updated last month
- Solutions to the Google foobar challenges made to me☆12Jun 6, 2022Updated 4 years ago
- This is a circular buffer controller used in FPGA.☆36Jan 12, 2016Updated 10 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Oct 9, 2019Updated 6 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆19Jun 15, 2026Updated 2 months ago
- 一个JPEG有损图像压缩编码器☆13May 22, 2023Updated 3 years ago
- RockerIC verification V1 series Labs☆18Mar 24, 2026Updated 4 months ago
- Various projects of SPI loader module for xilinx fpga☆34Jul 20, 2020Updated 6 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Jul 8, 2013Updated 13 years ago
- ☆38Mar 10, 2021Updated 5 years ago
- LMS sound filtering by Verilog☆43Apr 5, 2020Updated 6 years ago
- ☆25May 9, 2019Updated 7 years ago
- 基于verilog实现了ISP图像处理IP(Altera EP4CE6)☆25Jul 15, 2022Updated 4 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Code for the paper "Overconfidence is a Dangerous Thing: Mitigating Membership Inference Attacks by Enforcing Less Confident Prediction" …☆13Sep 6, 2023Updated 2 years ago
- 10_100_1000 Mbps tri-mode ethernet MAC☆11Jul 17, 2014Updated 12 years ago
- 一种基于FPGA平台的实时视频去雾系统项目代码，其中bit流文件可以直接下载到PYNQ-Z2开发板上，通过usb和hdmi设备输入有雾视频，将去雾后的视频输出到显示屏上。c++源代码部分是我们的去雾IP核的源代码。☆21Nov 24, 2019Updated 6 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- Projects for the ECPiX-5 - a ECP5 FPGA board.☆14Jul 5, 2020Updated 6 years ago
- Create a variety of wonderful fractals and curves in Typst☆19May 11, 2025Updated last year
- BlueDBM hw/sw implementation using the bluespecpcie PCIe library☆12Dec 25, 2022Updated 3 years ago
- This repository contains the code for our ECCV 2022 paper on our "Non-isotropic Probabilistic Take on Proxy-based Deep Metric Learning".☆12Dec 6, 2022Updated 3 years ago
- Firmware that implements a reliable high-performance control link for particle physics electronics, based on the IPbus protocol☆44Mar 5, 2026Updated 5 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆10Nov 8, 2019Updated 6 years ago
- (OBSOLETE) OSPFN Version 2.0☆15Mar 28, 2018Updated 8 years ago
- Wi-Fi LDPC codec Verilog IP core☆20Jun 30, 2026Updated last month
- BCH (Bose-Chaudhuri-Hocquenghem) encoder and decoder built from scratch in matlab as course project for EE5160: Error Control Coding☆18Mar 31, 2017Updated 9 years ago
- ☆17Jul 9, 2017Updated 9 years ago
- A LiteX module implementing a USB UAC2 module with simple PDM in/out☆16Feb 16, 2022Updated 4 years ago
- ELVE : ELVE Logic Visualization Engine☆11Jul 2, 2017Updated 9 years ago