ipcoregarfield / Example-Codes-for-Snorkeling-in-Verilog-BayView external linksLinks
Example Codes for Snorkeling in Verilog Bay
☆16Sep 9, 2016Updated 9 years ago
Alternatives and similar repositories for Example-Codes-for-Snorkeling-in-Verilog-Bay
Users that are interested in Example-Codes-for-Snorkeling-in-Verilog-Bay are comparing it to the libraries listed below
Sorting:
- a multiplier÷r verilog RTL file for RV32M instructions☆14Mar 17, 2020Updated 5 years ago
- unsigned Radix-2 SRT division,基2 除法☆16May 12, 2015Updated 10 years ago
- ASIC Design of the openSPARC Floating Point Unit☆15Mar 13, 2017Updated 8 years ago
- ☆19Aug 10, 2020Updated 5 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Oct 9, 2019Updated 6 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Jul 8, 2013Updated 12 years ago
- There are the documents, floating and fixed-point algorithms, and Verilog codes for the project.☆11Jun 27, 2016Updated 9 years ago
- Gaussian noise generator Verilog IP core☆32May 22, 2023Updated 2 years ago
- 10_100_1000 Mbps tri-mode ethernet MAC☆10Jul 17, 2014Updated 11 years ago
- This is a circular buffer controller used in FPGA.☆34Jan 12, 2016Updated 10 years ago
- BlueDBM hw/sw implementation using the bluespecpcie PCIe library☆12Dec 25, 2022Updated 3 years ago
- Public repository of the UCSC CMPE220 class project☆10Oct 8, 2017Updated 8 years ago
- ELVE : ELVE Logic Visualization Engine☆11Jul 2, 2017Updated 8 years ago
- fpga i2c slave verilog hdl rtl☆16Nov 26, 2015Updated 10 years ago
- RTL Design and Implementation of High Performance Algorithm Logic Units☆15Oct 1, 2019Updated 6 years ago
- A Fractional Divider with Delta-Sigma Modulator and Dual-Mode Divider for Phase-Locked Loop☆16Apr 25, 2021Updated 4 years ago
- ☆12Aug 26, 2016Updated 9 years ago
- LMS sound filtering by Verilog☆43Apr 5, 2020Updated 5 years ago
- ☆12Sep 8, 2017Updated 8 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- The source code that empowers OpenROAD Cloud☆12Jun 29, 2020Updated 5 years ago
- ☆11Apr 22, 2025Updated 9 months ago
- Recipe for FPGA cooking☆11Mar 15, 2019Updated 6 years ago
- 位 宽和深度可定制的异步FIFO☆13May 29, 2024Updated last year
- RISC-V RV32I CPU written in verilog☆10Jul 11, 2020Updated 5 years ago
- ☆10Feb 27, 2020Updated 5 years ago
- RISC-V System on Chip Builder☆12Sep 27, 2020Updated 5 years ago
- FISC - Flexible Instruction Set Computer - Is the new Instruction Set Architecture inspired by ARMv8 and x86-64☆15Aug 22, 2019Updated 6 years ago
- The ANUBIS benchmark suite for Incremental Synthesis☆12Dec 15, 2020Updated 5 years ago
- Business Rule Engine Hardware Accelerator☆14Jun 18, 2020Updated 5 years ago
- MT29F128G based NAND flash controller☆10Jun 17, 2021Updated 4 years ago
- Solutions to the Google foobar challenges made to me☆12Jun 6, 2022Updated 3 years ago
- 开发环境是Windows 10, Quartus。硬件开发语言是Verilog。 利用FPGA开发的智能小车,分为两个部分,控制器部分和小车部分,通过蓝牙信号进行连接。 控制部分可以通过加速度传感器检测手势,从而控制小车的前后左右。 加速度传感器还可以检测人体是否摔倒…☆13Mar 10, 2019Updated 6 years ago
- A simple implementation of the Karatsuba multiplication algorithm☆11Apr 2, 2025Updated 10 months ago
- Circuit Synthesis for Yao's Garbled Circuit by TinyGarble☆11Sep 25, 2020Updated 5 years ago
- ☆11Jun 6, 2021Updated 4 years ago
- Repository containing the DSP gateware cores☆14Feb 6, 2026Updated last week
- An example Hardware Processing Engine☆12Feb 4, 2023Updated 3 years ago
- RISC-V 32-bit core for MCCI Catena 4710☆10Jul 31, 2019Updated 6 years ago