Example Codes for Snorkeling in Verilog Bay
☆16Sep 9, 2016Updated 9 years ago
Alternatives and similar repositories for Example-Codes-for-Snorkeling-in-Verilog-Bay
Users that are interested in Example-Codes-for-Snorkeling-in-Verilog-Bay are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- unsigned Radix-2 SRT division,基2除法☆16May 12, 2015Updated 10 years ago
- a multiplier÷r verilog RTL file for RV32M instructions☆14Mar 17, 2020Updated 6 years ago
- ASIC Design of the openSPARC Floating Point Unit☆15Mar 13, 2017Updated 9 years ago
- There are the documents, floating and fixed-point algorithms, and Verilog codes for the project.☆11Jun 27, 2016Updated 9 years ago
- ☆11Jun 6, 2021Updated 4 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Automatically exported from code.google.com/p/asy4cn☆11Jul 11, 2022Updated 3 years ago
- fpga i2c slave verilog hdl rtl☆16Nov 26, 2015Updated 10 years ago
- An attempt to synthesize GPS signals in FPGA logic.☆20Feb 17, 2026Updated last month
- ☆19Aug 10, 2020Updated 5 years ago
- Solutions to the Google foobar challenges made to me☆12Jun 6, 2022Updated 3 years ago
- Gaussian noise generator Verilog IP core☆33May 22, 2023Updated 2 years ago
- This is a circular buffer controller used in FPGA.☆35Jan 12, 2016Updated 10 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Oct 9, 2019Updated 6 years ago
- Create a variety of wonderful fractals and curves in Typst☆17May 11, 2025Updated 10 months ago
- NordVPN Special Discount Offer • AdSave on top-rated NordVPN 1 or 2-year plans with secure browsing, privacy protection, and support for for all major platforms.
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Jul 8, 2013Updated 12 years ago
- 一个JPEG有损图像压缩编码器☆13May 22, 2023Updated 2 years ago
- Various projects of SPI loader module for xilinx fpga☆33Jul 20, 2020Updated 5 years ago
- 一种基于FPGA平台的实时视频去雾系统项目代码,其中bit流文件可以直接下载到PYNQ-Z2开发板上,通过usb和hdmi设备输入有雾视频,将去雾后的视频输出到显示屏上。c++源代码部分是我们的去雾IP核的源代码。☆20Nov 24, 2019Updated 6 years ago
- LMS sound filtering by Verilog☆43Apr 5, 2020Updated 5 years ago
- ☆17Jul 9, 2017Updated 8 years ago
- 10_100_1000 Mbps tri-mode ethernet MAC☆10Jul 17, 2014Updated 11 years ago
- Code for the paper "Overconfidence is a Dangerous Thing: Mitigating Membership Inference Attacks by Enforcing Less Confident Prediction" …☆12Sep 6, 2023Updated 2 years ago
- 基于verilog实现了ISP图像处理IP(Altera EP4CE6)☆22Jul 15, 2022Updated 3 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- ☆25May 9, 2019Updated 6 years ago
- This repository contains the code for our ECCV 2022 paper on our "Non-isotropic Probabilistic Take on Proxy-based Deep Metric Learning".☆12Dec 6, 2022Updated 3 years ago
- BlueDBM hw/sw implementation using the bluespecpcie PCIe library☆12Dec 25, 2022Updated 3 years ago
- Firmware that implements a reliable high-performance control link for particle physics electronics, based on the IPbus protocol☆43Mar 5, 2026Updated 3 weeks ago
- Wi-Fi LDPC codec Verilog IP core☆19Oct 20, 2019Updated 6 years ago
- ☆10Nov 8, 2019Updated 6 years ago
- Projects for the ECPiX-5 - a ECP5 FPGA board.☆14Jul 5, 2020Updated 5 years ago
- BCH (Bose-Chaudhuri-Hocquenghem) encoder and decoder built from scratch in matlab as course project for EE5160: Error Control Coding☆18Mar 31, 2017Updated 8 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- ☆21May 9, 2025Updated 10 months ago
- A LiteX module implementing a USB UAC2 module with simple PDM in/out☆16Feb 16, 2022Updated 4 years ago
- ELVE : ELVE Logic Visualization Engine☆11Jul 2, 2017Updated 8 years ago
- Scripts to build TinyAstro image☆21May 13, 2016Updated 9 years ago
- Xilinx IP repository☆13May 5, 2018Updated 7 years ago
- VSH(SHell for Visualizing vcd file)项目为数字波形文件命令行查看器。☆25Dec 8, 2025Updated 3 months ago
- ☆12Sep 8, 2017Updated 8 years ago